A Novel Prototype for Obstacle Detection and Relative Speed Control of an Automotive Using CPLD. - Ketan J. Raut; Pankaj Bande; Manish M. Patil (ICETET, 2008)

Novel integrated development environment for implementing PLC on FPGA by converting ladder diagram to synthesizable VHDL code. - Shaila Subbaraman; Manish M. Patil; Prashant S. Nilkund (ICARCV, 2010)

Exploring Integrated Circuit Verification Methodology for Verification and Validation of PLC Systems. - Manish M. Patil; Shaila Subbaraman; Shirish Joshi (ISED, 2011)