A New Approach to Analyze a Sub-micron CMOS Inverter. - Manisha Pattanaik; Swapna Banerjee (VLSI Design, 2003)

Performance Analysis of 90nm Look Up Table (LUT) for Low Power Application. - Deepak Kumar; Pankaj Kumar; Manisha Pattanaik (DSD, 2010)

An Efficient Compressed Domain Spatial Transcoding Scheme for Adaptive Video Content Delivery. - Nishant Khanwalkar; Shashikala Tapaswi; Manisha Pattanaik (PCM (2), 2010)

Performance analysis of dynamic threshold MOS (DTMOS) based 4-input multiplexer switch for low power and high speed FPGA design. - Deepak Kumar; Pankaj Kumar; Manisha Pattanaik (SBCCI, 2010)

An efficient image noise removal and enhancement method. - Nafis Uddin Khan; K. V. Arya; Manisha Pattanaik (SMC, 2010)

A Novel Low Power Noise Tolerant High Performance Dynamic Feed through Logic Design Technique. - Manisha Pattanaik; Shashank Parashar; Chaudhry Indra Kumar; Akanksha Chouhan; Vikas Mahor (ISED, 2011)

An Efficient Design Technique for High Performance Dynamic Feedthrough Logic with Enhanced Noise Tolerance. - Shashank Parashar; Chaudhry Indra Kumar; Manisha Pattanaik (ISVLSI, 2011)

A New Adaptive Thresholding in SVD for Efficient Image De-noising. - Nafis Uddin Khan; K. V. Arya; Manisha Pattanaik (SocProS (2), 2011)

Stability and Leakage Analysis of a Novel PP Based 9T SRAM Cell Using N Curve at Deep Submicron Technology for Multimedia Applications. - Shilpi Birla; Rakesh Kumar Singh; Manisha Pattanaik (Circuits Syst., 2011)

Analysis of 8T SRAM Cell at Various Process Corners at 65 nm Process Technology. - Shilpi Birla; Neeraj Kumar Shukla; Kapil Rathi; Rakesh Kumar Singh; Manisha Pattanaik (Circuits Syst., 2011)

Advancement in Nanoscale CMOS Device Design En Route to Ultra-Low-Power Applications. - Subhra Dhar; Manisha Pattanaik; Poolla Rajaram (VLSI Design, 2011)

Fuzzy based diffusion coefficient function in anisotropic diffusion for impulse noise removal. - Nafis Uddin Khan; K. V. Arya; Manisha Pattanaik (ICVGIP, 2012)

A New Assist Technique to Enhance the Read and Write Margins of Low Voltage SRAM Cell. - Santhosh Keshavarapu; Saumya Jain; Manisha Pattanaik (ISED, 2012)

A Process Variation Tolerant Low Contention Keeper Design for Wide Fan-In Dynamic OR Gate. - Vikas Mahor; Akanksha Chouhan; Manisha Pattanaik (ISED, 2012)

Signal Stepping Based Multimode Multi-threshold CMOS Technique for Ground Bounce Noise Reduction in Static CMOS Adders. - Shashikant Sharma; Manisha Pattanaik; Balwinder Raj (ISED, 2012)

Double-gate FinFET process variation aware 10T SRAM cell topology design and analysis. - Nandakishor Yadav; Sunil Dutt; Manisha Pattanaik; G. K. Sharma 001 (ECCTD, 2013)

Histogram statistics based variance controlled adaptive threshold in anisotropic diffusion for low contrast image enhancement. - Nafis Uddin Khan; K. V. Arya; Manisha Pattanaik (Signal Process., 2013)

NBTI aware IG-FinFET based SRAM design using adaptable trip-point sensing technique. - Nandakishor Yadav; Shikha Jain; Manisha Pattanaik; G. K. Sharma 001 (NANOARCH, 2014)

TID effects on retention of 0.13 μm SONOS memory cell: A device simulation approach. - Shipra Bassi; Manisha Pattanaik (VDAT, 2014)

Operation-aware assist circuit design for improved write performance of FinFET based SRAM. - Ekta Prajapati; Nandakishor Yadav; Manisha Pattanaik; G. K. Sharma 001 (VDAT, 2014)

Techniques for Low Leakage nanoscale VLSI Circuits: a Comparative Study. - Vijay Kumar Sharma; Manisha Pattanaik (J. Circuits Syst. Comput., 2014)

Process, Voltage and Temperature Variations Aware Low Leakage Approach for Nanoscale CMOS Circuits. - Vijay Kumar Sharma; Manisha Pattanaik (J. Low Power Electron., 2014)

Parameter variation aware hybrid TFET-CMOS based power gating technique with a temperature variation tolerant sleep mode. - Abhishek Mishra; Kamal Kishor Jha; Manisha Pattanaik (Microelectron. J., 2014)

PVT variations aware low leakage INDEP approach for nanoscale CMOS circuits. - Vijay Kumar Sharma; Manisha Pattanaik; Balwinder Raj (Microelectron. Reliab., 2014)

Edge preservation of impulse noise filtered images by improved anisotropic diffusion. - Nafis Uddin Khan; K. V. Arya; Manisha Pattanaik (Multim. Tools Appl., 2014)

High Performance Process Variations Aware Technique for Sub-threshold 8T-SRAM Cell. - Vijay Kumar Sharma; Sumit Patel; Manisha Pattanaik (Wirel. Pers. Commun., 2014)

A novel dual multiplier floating point multiply accumulate architecture. - Rohit Kumar; Manisha Pattanaik (VDAT, 2015)

Performance study of side block oxide band gap engineered SONOS: A device simulation approach. - Gagan Deep Verma; Manisha Pattanaik (VDAT, 2015)

Low Leakage and Highly Noise Immune FinFET-Based Wide Fan-In Dynamic Logic Design. - Vikas Mahor; Manisha Pattanaik (J. Circuits Syst. Comput., 2015)

Novel NBTI Aware Approach for Low Power FinFET Based Wide Fan-In Domino Logic. - Vikas Mahor; Manisha Pattanaik (J. Low Power Electron., 2015)

New Topology Approach for Future Process, Voltage and Temperature Aware SRAM Using Independently Controlled Double-Gate FinFET. - Nandakishor Yadav; Manisha Pattanaik; G. K. Sharma 001 (J. Low Power Electron., 2015)

A novel stability and process sensitivity driven model for optimal sized FinFET based SRAM. - Nandakishor Yadav; Shikha Jain; Manisha Pattanaik; G. K. Sharma 001 (Microelectron. Reliab., 2015)

Low Stand-By Power and Process Variation Tolerant FinFET Based SRAM Cell. - Akanksha Bhadoria; Mukesh Chaturvedi; Vikas Mahor; Manisha Pattanaik (iNIS, 2016)

FinFET-Based Low Power Address Decoder under Process Variation. - Mukesh Chaturvedi; Akanksha Bhadoria; Vikas Mahor; Manisha Pattanaik (iNIS, 2016)

Novel Ultra Low Leakage FinFET Based SRAM Cell. - Vivek Kumar; Vikas Mahor; Manisha Pattanaik (iNIS, 2016)

Design of Low Leakage Variability Aware ONOFIC CMOS Standard Cell Library. - Vijay Kumar Sharma; Manisha Pattanaik (J. Circuits Syst. Comput., 2016)

Design and Analysis of Schmitt Trigger Based 10T SRAM in 32 nm Technology. - Amit Singh Rajput; Manisha Pattanaik; Ritesh Kumar Tiwari (iNIS, 2017)

An Aging-Aware Reliable FinFET-Based Low-Power 32-Word ( times ) 32-bit Register File. - Vikas Mahor; Manisha Pattanaik (Circuits Syst. Signal Process., 2017)

Low Leakage Noise Tolerant 10T SRAM Cell. - Vinay Gupta; Pratiksha Shukla; Manisha Pattanaik (VDAT, 2018)

Low Leakage Read Write Enhanced 9T SRAM Cell. - Pratiksha Shukla; Vinay Gupta; Manisha Pattanaik (VDAT, 2018)

A State-of-the-Art Current Mirror-Based Reliable Wide Fan-in FinFET Domino OR Gate Design. - Vikas Mahor; Manisha Pattanaik (Circuits Syst. Signal Process., 2018)

Semantic Image Completion and Enhancement using Deep Learning. - Vaishnav Chandak; Priyansh Saxena; Manisha Pattanaik; Gaurav Kaushal (ICCCNT, 2019)

Quality Driven Energy Aware Approximated Core Transform Architecture for HEVC Standard. - Neelam Arya; Anil Kumar Rajput; Manisha Pattanaik; G. K. Sharma 001 (VDAT, 2019)

Energy Efficient 9T SRAM With R/W Margin Enhanced for beyond Von-Neumann Computation. - Anil Kumar Rajput; Manisha Pattanaik (VDAT, 2020)

A New Hardware Trojan Detection Technique using Class Weighted XGBoost Classifier. - Richa Sharma; Nitya Kritin Valivati; G. K. Sharma 001; Manisha Pattanaik (VDAT, 2020)

Area and Energy Efficient Approximate Square Rooters for Error Resilient Applications. - Neelam Arya; Teena Soni; Manisha Pattanaik; G. K. Sharma 001 (VLSID, 2020)

Reduction of Drain Induced Barrier Lowering in DM-HD-NA GAAFET for RF Applications. - Amit Kumar; Manisha Pattanaik; Pankaj Srivastava; Kamal Kishor Jha (IET Circuits Devices Syst., 2020)

Bit significance based reconfigurable approximate restoring dividers and square rooters. - Neelam Arya; Teena Soni; Manisha Pattanaik; G. K. Sharma 001 (Microelectron. J., 2020)

A Few Shot Learning based Approach for Hardware Trojan Detection using Deep Siamese CNN. - Richa Sharma; G. K. Sharma 001; Manisha Pattanaik (VLSID, 2021)

READ: A fixed restoring array based accuracy-configurable approximate divider for energy efficiency. - Neelam Arya; Teena Soni; Manisha Pattanaik; G. K. Sharma 001 (Integr., 2021)

A new hardware Trojan detection technique using deep convolutional neural network. - Richa Sharma; Vijaypal Singh Rathor; G. K. Sharma 001; Manisha Pattanaik (Integr., 2021)

Energy-Efficient Logarithmic Square Rooter for Error-Resilient Applications. - Neelam Arya; Manisha Pattanaik; G. K. Sharma 001 (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Local bit-line shared pass-gate 8T SRAM based energy efficient and reliable In-Memory Computing architecture. - Anil Kumar Rajput; Manisha Pattanaik; Gaurav Kaushal (Microelectron. J., 2022)

Energy efficient logarithmic-based approximate divider for ASIC and FPGA-based implementations. - Neelam Arya; Teena Soni; Manisha Pattanaik; G. K. Sharma 001 (Microprocess. Microsystems, 2022)

Coverage hole detection using social spider optimized Gaussian Mixture Model. - Abhishek Gupta; Somesh Kumar; Manisha Pattanaik (J. King Saud Univ. Comput. Inf. Sci., 2022)

A CatBoost Based Approach to Detect Label Flipping Poisoning Attack in Hardware Trojan Detection Systems. - Richa Sharma; G. K. Sharma 001; Manisha Pattanaik (J. Electron. Test., 2022)

Novel Label Flipping Dataset Poisoning Attack Against ML-Based HT Detection Systems. - Richa Sharma; G. K. Sharma 001; Manisha Pattanaik (APCCAS, 2023)

An Energy-Efficient and Robust 10T SRAM Based in-Memory Computing Architecture. - Noopur Srivastava; Anil Kumar Rajput; Manisha Pattanaik; Gaurav Kaushal (VLSID, 2023)

Local bit line 8T SRAM based in-memory computing architecture for energy-efficient linear error correction codec implementation. - Anil Kumar Rajput; Manisha Pattanaik (Microelectron. J., 2023)

An Energy-Efficient Hybrid SRAM-Based In-Memory Computing Macro for Artificial Intelligence Edge Devices. - Anil Kumar Rajput; Alok Kumar Tiwari; Manisha Pattanaik (Circuits Syst. Signal Process., 2023)

Structural and SCOAP Features Based Approach for Hardware Trojan Detection Using SHAP and Light Gradient Boosting Model. - Richa Sharma; G. K. Sharma 001; Manisha Pattanaik; V. S. S. Prashant (J. Electron. Test., 2023)

Adversarial Label Flipping Attack on Supervised Machine Learning-Based HT Detection Systems. - Richa Sharma; G. K. Sharma 001; Manisha Pattanaik (ISCAS, 2024)

Effect of Fog Particle Size Distribution on 3D Object Detection Under Adverse Weather Conditions. - Ajinkya Shinde; Gaurav Sharma; Manisha Pattanaik; Sri Niwas Singh (CoRR, 2024)

Radiation Hardened by Design-based Voltage Controlled Oscillator for Low Power Phase Locked Loop Application. - Rachana Ahirwar; Manisha Pattanaik; Pankaj Srivastava (J. Electron. Test., 2024)

Investigating and Improving the Performance of Radiation-Hardened SRAM Cell with the Use of Multi-Voltage Transistors. - Rachana Ahirwar; Manisha Pattanaik; Pankaj Srivastava (J. Electron. Test., 2024)

Low-light DEtection TRansformer (LDETR): object detection in low-light and adverse weather conditions. - Alok Kumar Tiwari; Manisha Pattanaik; G. K. Sharma 001 (Multim. Tools Appl., 2024)

Sparse Channel Estimation for Hybrid MIMO Millimeter Wave Communication Impaired by Impulsive Noise. - Dhruv Sanghvi; Sandesh Jain; Manisha Pattanaik; Vimal Bhatia (NCC, 2025)

BP-IMCA: An Energy-Efficient 8T SRAM-Based Bit-Parallel In-Memory Computing Architecture. - Anil Kumar Rajput; Manisha Pattanaik; Gaurav Kaushal (J. Circuits Syst. Comput., 2025)