Methodology to achieve planar technology-like ESD performance in FINFET process. - Jian-Hsing Lee; Manjunatha Prabhu; Konstantin Korablev; Jagar Singh; Mahadeva Iyer Natarajan; Shesh Mani Pandey (IRPS, 2015)

Printed-circuit board (PCB) charge induced product yield-loss during the final test. - Jian-Hsing Lee; Kunihiko Takahashi; Manjunatha Prabhu; Mahadeva Iyer Natarajan (IRPS, 2015)

Efficient Bidirectional protection structure for Plasma induced damage (PID) and Electrostatic discharge (ESD) for 3D IC Integration. - Premachandran CS; Salvatore Cimino; Manjunatha Prabhu (IRPS, 2020)