Model checking based analysis of end-to-end latency in embedded, real-time systems with clock drifts. - Swarup Mohalik; A. C. Rajeev; Manoj G. Dixit; S. Ramesh 002; P. Vijay Suman; Paritosh K. Pandya; Shengbing Jiang (DAC, 2008)

Taming the component timing: A CBD methodology for real-time embedded systems. - Manoj G. Dixit; Pallab Dasgupta; S. Ramesh 002 (DATE, 2010)

Schedulability and end-to-end latency in distributed ECU networks: formal modeling and precise estimation. - A. C. Rajeev; Swarup Mohalik; Manoj G. Dixit; Devesh B. Chokshi; S. Ramesh 002 (EMSOFT, 2010)

Some results on Parametric Temporal Logic. - Manoj G. Dixit; S. Ramesh 002; Pallab Dasgupta (Inf. Process. Lett., 2011)

Scalable model-checking for precise end-to-end latency computation. - Swarup Mohalik; Devesh B. Chokshi; Manoj G. Dixit; A. C. Rajeev; S. Ramesh 002 (CACSD, 2013)

Early Time-Budgeting for Component-Based Embedded Control Systems. - Manoj G. Dixit; S. Ramesh 002; Pallab Dasgupta (Embedded Systems Development, From Functional Models to Implementations, 2014)

Time-budgeting: a component based development methodology for real-time embedded systems. - Manoj G. Dixit; S. Ramesh 002; Pallab Dasgupta (Formal Aspects Comput., 2014)