Level Shifter Design for Low Power Applications - Manoj Kumar 005; Sandeep Kumar Arya; Sujata Pandey (CoRR, 2010)

Sequential combination of statistics, econometrics and Adaptive Neural-Fuzzy Interface for stock market prediction. - Tanvir Ansari; Manoj Kumar 005; Anupam Shukla; Joydip Dhar; Ritu Tiwari (Expert Syst. Appl., 2010)

Design of CMOS Energy Efficient Single Bit Full Adders. - Manoj Kumar 005; Sujata Pandey; Sandeep Kumar Arya (HPAGC, 2011)

Voltage Controlled Ring Oscillator Design with Novel 3 Transistors XNOR/XOR Gates. - Manoj Kumar 005; Sandeep Kumar Arya; Sujata Pandey (Circuits Syst., 2011)

Design of 9-transistor single bit full adder. - Manoj Kumar 005 (CCSEIT, 2012)

Single bit full adder design using 8 transistors with novel 3 transistors XNOR gate - Manoj Kumar 005; Sandeep Kumar Arya; Sujata Pandey (CoRR, 2012)

Modified 4-2 compressor using improved multiplexer for low power applications. - Dinesh Kumar; Manoj Kumar 005 (ICACCI, 2016)

Design of low power two bit magnitude comparator using adiabatic logic. - Dinesh Kumar; Manoj Kumar 005 (ISPACS, 2016)

Design of Linear Low-Power Voltage-Controlled Oscillator with I-MOS Varactor and Back-Gate Tuning. - Manoj Kumar 005 (Circuits Syst. Signal Process., 2018)

A Low Power CMOS-Based VCO Design with I-MOS Varactor Tuning Control. - Manoj Kumar 005; Dileep Dwivedi (J. Circuits Syst. Comput., 2018)

Comparative analysis of adiabatic logic challenges for low power CMOS circuit designs. - Dinesh Kumar; Manoj Kumar 005 (Microprocess. Microsystems, 2018)

Low Power, Ring VCO with Pre-Charge and Pre-Discharge Circuit for 4 GHz-6.1 GHz Applications in 0.18 μm CMOS. - Nitin Kumar 014; Manoj Kumar 005 (J. Circuits Syst. Comput., 2019)

A 3-14 GHz, Self-Body Biased Common-Gate UWB LNA for Wireless Applications in 90 nm CMOS. - Vikram Singh 006; Sandeep Kumar Arya; Manoj Kumar 005 (J. Circuits Syst. Comput., 2019)

Thermophoresis and suction/injection roles on free convective MHD flow of Ag-kerosene oil nanofluid. - Himanshu Upreti; Alok Kumar Pandey; Manoj Kumar 005 (J. Comput. Des. Eng., 2020)

Low power active load and IMOS varactor based VCO designs using differential delay stages in 0.18 ​μm technology. - Vivek Jangra; Manoj Kumar 005 (Microelectron. J., 2020)

Low Power XNOR based Single Ended VCO Circuit Design with Dynamic Threshold MOS. - Vivek Jangra; Manoj Kumar 005 (IC3, 2021)

Low power CMOS differential ring VCO designs using dual delay stages in 0.13 ​μm technology for wireless applications. - Nitin Kumar 014; Manoj Kumar 005 (Microelectron. J., 2021)

A Common-Gate Current-Reuse UWB LNA for Wireless Applications in 90 nm CMOS. - Vikram Singh 006; Sandeep Kumar Arya; Manoj Kumar 005 (Wirel. Pers. Commun., 2021)

A PVT tolerant low power wide tuning range differential voltage controlled oscillator design in 90 nm CMOS technology. - Vivek Jangra; Manoj Kumar 005 (Integr., 2023)

Design of Low Power CMOS based Array Multiplier in 90nm Technology. - Tejaswi Chetamoni; Mothe Rishi; Manoj Kumar 005 (ICCCNT, 2024)

Design of a low power LNA circuit with noise canceling approach in 90 nm CMOS process. - Vikram Singh 006; Manoj Kumar 005; Nitin Kumar 014 (Integr., 2024)

Design of CMOS VCO with XNOR and transmission gate based delay stages. - Manoj Kumar 005; Priyanshu Lakra (Integr., 2025)