A Metric of Tolerance for the Manufacturing Defects of Threshold Logic Gates. - Sandeep Dechu; Manoj Kumar Goparaju; Spyros Tragoudas (DFT, 2006)

A Fault Tolerant Design Methodology for Threshold Logic Gates and Its Optimizations. - Manoj Kumar Goparaju; Spyros Tragoudas (ISQED, 2007)

A Fault Tolerance Aware Synthesis Methodology for Threshold Logic Gate Networks. - Manoj Kumar Goparaju; Ashok Kumar Palaniswamy; Spyros Tragoudas (DFT, 2008)

A Novel ATPG Framework to Detect Weight Related Defects in Threshold Logic Gates. - Manoj Kumar Goparaju; Spyros Tragoudas (VTS, 2008)

Scalable identification of threshold logic functions. - Ashok Kumar Palaniswamy; Manoj Kumar Goparaju; Spyros Tragoudas (ACM Great Lakes Symposium on VLSI, 2010)