Catastrophic Defects Oriented Testability Analysis of a Class AB Amplifier. - Manoj Sachdev (DFT, 1993)

Development of Fault Model and Test Algorithms for Embedded DRAMs. - Manoj Sachdev; Math Verstraelen (ITC, 1993)

Comments on 'Totally self-checking CMOS circuit design for breaks and stuck-on faults'. - Eric Bruls; Manoj Sachdev; Keith Baker (IEEE J. Solid State Circuits, 1993)

Transforming Sequential Logic in Digital CMOS ICs for Voltage and IDDQ Testing. - Manoj Sachdev (EDAC-ETC-EUROASIC, 1994)

Defect-oriented test methodology for complex mixed-signal circuits. - F. C. M. Kuijstermans; Manoj Sachdev; A. P. Thijssen (ED&TC, 1995)

IDDQ and Voltage Testable CMOS Flip-flop Configurations. - Manoj Sachdev (ITC, 1995)

Industrial Relevance of Analog IFA: A Fact or a Fiction. - Manoj Sachdev; Bert Atzema (ITC, 1995)

Testing Defects in Scan Chains. - Manoj Sachdev (IEEE Des. Test Comput., 1995)

Reducing the CMOS RAM test complexity withIDDQ and voltage testing. - Manoj Sachdev (J. Electron. Test., 1995)

A realistic defect oriented testability methodology for analog circuits. - Manoj Sachdev (J. Electron. Test., 1995)

Test and Testability Techniques for Open Defects in RAM Address Decoders. - Manoj Sachdev (ED&TC, 1996)

Low power, testable dual edge triggered flip-flops. - Rafael Llopis; Manoj Sachdev (ISLPED, 1996)

Deep Sub-micron IDDQ Test Options. - Manoj Sachdev (ITC, 1996)

SeparateIDDQ testing of signal and bias paths in CMOS ICs for defect diagnosis. - Manoj Sachdev (J. Electron. Test., 1996)

Deep sub-micron IDDQ testing: issues and solutions. - Manoj Sachdev (ED&TC, 1997)

Open Defects in CMOS RAM Address Decoders. - Manoj Sachdev (IEEE Des. Test Comput., 1997)

Defect detection with transient current testing and its potential for deep sub-micron CMOS ICs. - Manoj Sachdev; Peter Janssen; Victor Zieren (ITC, 1998)

A DFT technique for high performance circuit testing. - Mansour Shashaani; Manoj Sachdev (ITC, 1999)

Configurations for IDDQ-Testable PLAs. - Manoj Sachdev; Hans G. Kerkhoff (IEEE Des. Test Comput., 1999)

Off-Chip Diagnosis of Aperture Jitter in Full-Flash Analog-to-Digital Converters. - Richard Rosing; Hans G. Kerkhoff; Ronald J. W. T. Tangelder; Manoj Sachdev (J. Electron. Test., 1999)

Bridging the testing speed gap: design for delay testability. - Han Speek; Hans G. Kerkhoff; Manoj Sachdev; Mansour Shashaani (ETW, 2000)

Multiple-parameter CMOS IC testing with increased sensitivity for I_DDQ. - Ali Keshavarzi; Kaushik Roy 001; Charles F. Hawkins; Manoj Sachdev; Krishnamurthy Soumyanath; Vivek De (ITC, 2000)

A Low-Speed BIST Framework for High-Performance Circuit Testing. - Hans G. Kerkhoff; Mansour Shashaani; Manoj Sachdev (VTS, 2000)

Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors. - James W. Tschanz; Siva G. Narendra; Zhanping Chen; Shekhar Borkar; Manoj Sachdev; Vivek De (ISLPED, 2001)

A Methodology for Testing High-Performance Circuits at Arbitrarily Low Test Frequency. - Muhammad Nummer; Manoj Sachdev (VTS, 2001)

Current-Based Testing for Deep-Submicron VLSIs. - Manoj Sachdev (IEEE Des. Test Comput., 2001)

Design for Delay Testability in High-Speed Digital ICs. - Hans G. Kerkhoff; Han Speek; M. Shashani; Manoj Sachdev (J. Electron. Test., 2001)

Effect of Static Power Dissipation in Burn-In Environment on Yield of VLSI. - Arman Vassighi; Oleg Semenov; Manoj Sachdev; Ali Keshavarzi (DFT, 2002)

A DFT Technique for Low Frequency Delay Fault Testing in High Performance Digital Circuits. - Bhaskar Chatterjee; Manoj Sachdev; Ali Keshavarzi (ITC, 2002)

Multi-Gigahertz Digital Test Challenges and Techniques. - Manoj Sachdev (ITC, 2002)

Trends and Challenges in VLSI Technology Scaling towards 100nm (Tutorial Abstract). - Stefan Rusu; Manoj Sachdev; Christer Svensson; Bram Nauta (ASP-DAC/VLSI Design, 2002)

Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits. - Ali Keshavarzi; James W. Tschanz; Siva G. Narendra; Vivek De; W. Robert Daasch; Kaushik Roy 001; Manoj Sachdev; Charles F. Hawkins (IEEE Des. Test Comput., 2002)

A comparative analysis of low-power low-voltage dual-edge-triggered flip-flops. - Wai Chung; Timothy Lo; Manoj Sachdev (IEEE Trans. Very Large Scale Integr. Syst., 2002)

DFT for Testing igh-Performance Pipelined Circuits with Slow-Speed Testers. - Muhammad Nummer; Manoj Sachdev (DATE, 2003)

Thermal Management of High Performance Microprocessors. - Arman Vassighi; Oleg Semenov; Manoj Sachdev; Ali Keshavarzi (DFT, 2003)

Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies. - Bhaskar Chatterjee; Manoj Sachdev; Steven Hsu; Ram Krishnamurthy 001; Shekhar Borkar (ISLPED, 2003)

Burn-in Temperature Projections for Deep Sub-micron Technologies. - Oleg Semenov; Arman Vassighi; Manoj Sachdev; Ali Keshavarzi; Charles F. Hawkins (ITC, 2003)

Transistor-Level Fault Analysis and Test Algorithm Development for Ternary Dynamic Content Addressable Memorie. - Derek Wright; Manoj Sachdev (ITC, 2003)

A DFT Technique for Testing High-Speed Circuits with Arbitrarily Slow Testers. - Muhammad Nummer; Manoj Sachdev (J. Electron. Test., 2003)

Leakage Current in Sub-Quarter Micron MOSFET: A Perspective on Stressed Delta IDDQ Testing. - Oleg Semenov; Arman Vassighi; Manoj Sachdev (J. Electron. Test., 2003)

Testing high-performance pipelined circuits with slow-speed testers. - Muhammad Nummer; Manoj Sachdev (ACM Trans. Design Autom. Electr. Syst., 2003)

A digitally programmable delay element: design and analysis. - Mohammad Maymandi-Nejad; Manoj Sachdev (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Design optimizations for microprocessors at low temperature. - Arman Vassighi; Ali Keshavarzi; Siva G. Narendra; Gerhard Schrom; Yibin Ye; Seri Lee; Greg Chrysler; Manoj Sachdev; Vivek De (DAC, 2004)

Modeling and designing energy-delay optimized wide domino circuits. - Christine Kwong; Bhaskar Chatterjee; Manoj Sachdev (ISCAS (2), 2004)

Low power dual matchline ternary content addressable memory. - Nitin Mohan; Manoj Sachdev (ISCAS (2), 2004)

A CPL-based dual supply 32-bit ALU for sub 180nm CMOS technologies. - Bhaskar Chatterjee; Manoj Sachdev; Ram Krishnamurthy 001 (ISLPED, 2004)

Efficient adaptive voltage scaling system through on-chip critical path emulation. - Mohamed Elgebaly; Manoj Sachdev (ISLPED, 2004)

An Overview of Substrate Noise Reduction Techniques. - Shahab Ardalan; Manoj Sachdev (ISQED, 2004)

Leakage Control Techniques for Designing Robust, Low Power Wide-OR Domino Logic for sub-130 nm CMOS Technologies. - Bhaskar Chatterjee; Manoj Sachdev; Ram Krishnamurthy 001 (ISQED, 2004)

A DFT Technique for Delay Fault Testability and Diagnostics in 32-Bit High Performance CMOS ALUs. - Bhaskar Chatterjee; Manoj Sachdev; Ali Keshavarzi (ITC, 2004)

AN SRAM Weak Cell Fault Model and a DFT Technique with a Programmable Detection Threshold. - Andrei Pavlov; Manoj Sachdev; José Pineda de Gyvez (ITC, 2004)

DFT for Delay Fault Testing of High-Performance Digital Circuits. - Bhaskar Chatterjee; Manoj Sachdev; Ali Keshavarzi (IEEE Des. Test Comput., 2004)

An analytical equation for the oscillation frequency of high-frequency ring oscillators. - Stephen Docking; Manoj Sachdev (IEEE J. Solid State Circuits, 2004)

Evaluation of STI degradation using temperature dependence of leakage current in parasitic STI MOSFET. - Oleg Semenov; Michael S. Obrecht; Manoj Sachdev (Microelectron. Reliab., 2004)

The Impact of CMOS technology scaling on MOSFETs second breakdown: Evaluation of ESD robustness. - Oleg Semenov; Hossein Sarbishaei; Valery Axelrad; Manoj Sachdev (Microelectron. Reliab., 2004)

A low-power reduced swing global clocking methodology. - Farhad H. A. Asgari; Manoj Sachdev (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Correction to "A Digitally Programmable Delay Element: Design and Analysis". - Mohammad Maymandi-Nejad; Manoj Sachdev (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Programmable techniques for cell stability test and debug in embedded SRAMs. - Andrei Pavlov; Manoj Sachdev; José Pineda de Gyvez; Mohamed Azimane (CICC, 2005)

A 0.8V Delta-Sigma modulator using DTMOS technique. - Mohammad Maymandi-Nejad; Manoj Sachdev (ISCAS (4), 2005)

Analysis and Design of LVTSCR-based EOS/ESD Protection Circuits for Burn-in Environment. - Oleg Semenov; Hossein Sarbishaei; Manoj Sachdev (ISQED, 2005)

Word line pulsing technique for stability fault detection in SRAM cells. - Andrei Pavlov; Mohamed Azimane; José Pineda de Gyvez; Manoj Sachdev (ITC, 2005)

A monotonic digitally controlled delay element. - Mohammad Maymandi-Nejad; Manoj Sachdev (IEEE J. Solid State Circuits, 2005)

Designing leakage tolerant, low power wide-OR dominos for sub-130nm CMOS technologies. - Bhaskar Chatterjee; Manoj Sachdev; Ram Krishnamurthy 001 (Microelectron. J., 2005)

Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology. - Bhaskar Chatterjee; Manoj Sachdev (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Match Line Sense Amplifiers with Positive Feedback for Low-Power Content Addressable Memories. - Nitin Mohan; Wilson Fung; Derek Wright; Manoj Sachdev (CICC, 2006)

A Phase-Domain Continuous-Time 2nd-Order ΔΣ Frequency Digitizer. - Mohammad Sharifkhani; Manoj Sachdev (CICC, 2006)

A phase-domain 2nd-order continuous time Delta-Sigma-modulator for frequency digitization. - Mohammad Sharifkhani; Manoj Sachdev (ISCAS, 2006)

A low power SRAM architecture based on segmented virtual grounding. - Mohammad Sharifkhani; Manoj Sachdev (ISLPED, 2006)

Dynamic Data Stability in SRAM Cells and Its Implications on Data Stability Tests. - Mohammad Sharifkhani; Shah M. Jahinuzzaman; Manoj Sachdev (MTDT, 2006)

Low-Power Priority Encoder and Multiple Match Detection Circuit for Ternary Content Addressable Memory. - Nitin Mohan; Wilson Fung; Manoj Sachdev (SoCC, 2006)

Novel Ternary Storage Cells and Techniques for Leakage Reduction in Ternary CAM. - Nitin Mohan; Manoj Sachdev (SoCC, 2006)

New JETTA Editors, 2006. - Bashir M. Al-Hashimi; Dimitris Gizopoulos; Manoj Sachdev; Adit D. Singh (J. Electron. Test., 2006)

Weak Cell Detection in Deep-Submicron SRAMs: A Programmable Detection Technique. - Andrei Pavlov; Manoj Sachdev; José Pineda de Gyvez (IEEE J. Solid State Circuits, 2006)

Novel gate and substrate triggering techniques for deep sub-micron ESD protection devices. - Oleg Semenov; Hossein Sarbishaei; Valery Axelrad; Manoj Sachdev (Microelectron. J., 2006)

DTMOS Technique for Low-Voltage Analog Circuits. - Mohammad Maymandi-Nejad; Manoj Sachdev (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Design techniques and test methodology for low-power TCAMs. - Nitin Mohan; Wilson Fung; Derek Wright; Manoj Sachdev (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Thermal and Power Management of Integrated Circuits - Arman Vassighi; Manoj Sachdev (Springer, 2006)

Optimizing Circuit Performance and ESD Protection for High-Speed Differential I/Os. - Hossein Sarbishaei; Oleg Semenov; Manoj Sachdev (CICC, 2007)

Dynamic Data Stability in Low-power SRAM Design. - Mohammad Sharifkhani; Shah M. Jahinuzzaman; Manoj Sachdev (CICC, 2007)

A Novel Tri-State Binary Phase Detector. - David Rennie; Manoj Sachdev (ISCAS, 2007)

Comparative Robustness of CML Phase Detectors for Clock and Data Recovery Circuits. - David Rennie; Manoj Sachdev (ISQED, 2007)

Low-Capacitance and Charge-Shared Match Lines for Low-Energy High-Performance TCAMs. - Nitin Mohan; Manoj Sachdev (IEEE J. Solid State Circuits, 2007)

Variation-Aware Adaptive Voltage Scaling System. - Mohamed Elgebaly; Manoj Sachdev (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Segmented Virtual Ground Architecture for Low-Power Embedded SRAM. - Mohammad Sharifkhani; Manoj Sachdev (IEEE Trans. Very Large Scale Integr. Syst., 2007)

A multiword based high speed ECC scheme for low-voltage embedded SRAMS. - Shah M. Jahinuzzaman; Tahseen Shakir; Sumanjit Lubana; Jaspal Singh Shah; Manoj Sachdev (ESSCIRC, 2008)

A fully digital ADC using a new delay element with enhanced linearity. - Hooman Farkhani; Mohammad Maymandi-Nejad; Manoj Sachdev (ISCAS, 2008)

Investigation of Process Impact on Soft Error Susceptibility of Nanometric SRAMs Using a Compact Critical Charge Model. - Shah M. Jahinuzzaman; Mohammad Sharifkhani; Manoj Sachdev (ISQED, 2008)

A 5-Gb/s CDR Circuit With Automatically Calibrated Linear Phase Detector. - David Rennie; Manoj Sachdev (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

ESD design challenges. - Manoj Sachdev; Hong-Ha Vuong (CICC, 2009)

ESD protection circuit for 8.5Gbps I/Os in 90nm CMOS technology. - Hossein Sarbishaei; Manoj Sachdev (CICC, 2009)

Design of a 64-bit Low-energy High-performance Adder using Dynamic Feedthrough Logic. - Pierce Chuang; David Li 002; Manoj Sachdev (ISCAS, 2009)

Design and Analysis of A 5.3-pJ 64-kb Gated Ground SRAM With Multiword ECC. - Shah M. Jahinuzzaman; Jaspal Singh Shah; David J. Rennie; Manoj Sachdev (IEEE J. Solid State Circuits, 2009)

SRAM Cell Stability: A Dynamic Perspective. - Mohammad Sharifkhani; Manoj Sachdev (IEEE J. Solid State Circuits, 2009)

An Energy Efficient 40 Kb SRAM Module With Extended Read/Write Noise Margin in 0.13 µm CMOS. - Mohammad Sharifkhani; Manoj Sachdev (IEEE J. Solid State Circuits, 2009)

A Low-Power Ternary CAM With Positive-Feedback Match-Line Sense Amplifiers. - Nitin Mohan; Wilson Fung; Derek Wright; Manoj Sachdev (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

An Analytical Model for Soft Error Critical Charge of Nanometric SRAMs. - Shah M. Jahinuzzaman; Mohammad Sharifkhani; Manoj Sachdev (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Low-Leakage Storage Cells for Ternary Content Addressable Memories. - Nitin Mohan; Manoj Sachdev (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Comparative analysis and study of metastability on high-performance flip-flops. - David Li 002; Pierce Chuang; Manoj Sachdev (ISQED, 2010)

Analysis of power supply noise mitigation circuits. - Tasreen Charania; Pierce Chuang; Ajoy Opal; Manoj Sachdev (CCECE, 2011)

Multiprocessor FPGA implementation of a 2D digital filter. - Danny Teng-Hsiang Tsuei; Mohamed-Yahia Dabbagh; Manoj Sachdev (CCECE, 2011)

Performance, metastability and soft-error robustness tradeoffs for flip-flops in 40nm CMOS. - David Rennie; David Li 002; Manoj Sachdev; Bharat L. Bhuva; Srikanth Jagannathan; Shi-Jie Wen; Rick Wong (CICC, 2011)

Design and analysis of metastable-hardened flip-flops in sub-threshold region. - David Li 002; Pierce Chuang; David Nairn; Manoj Sachdev (ISLPED, 2011)

Design and analysis of metastable-hardened and soft-error tolerant high-performance, low-power flip-flops. - David Li 002; David Rennie; Pierce Chuang; David Nairn; Manoj Sachdev (ISQED, 2011)

Digitally programmable SRAM timing for nano-scale technologies. - Adam Neale; Manoj Sachdev (ISQED, 2011)

Experimental Results for Slow-speed Timing Characterization of High-speed Pipelined Datapaths. - Muhammad Nummer; Manoj Sachdev (J. Electron. Test., 2011)

A Compact Hybrid Current/Voltage Sense Amplifier With Offset Cancellation for High-Speed SRAMs. - Mohammad Sharifkhani; Ehsan Rahiminejad; Shah M. Jahinuzzaman; Manoj Sachdev (IEEE Trans. Very Large Scale Integr. Syst., 2011)

A 148ps 135mW 64-bit adder with Constant-Delay logic in 65nm CMOS. - Pierce Chuang; David Li 002; Manoj Sachdev; Vincent C. Gaudet (CICC, 2012)

Power delivery: Droop, jitter, test and debug story (Tutorial). - Mike Li; Manoj Sachdev (CICC, 2012)

A word-line boost driver design for low operating voltage 6T-SRAMs. - Tahseen Shakir; Manoj Sachdev (MWSCAS, 2012)

A read-assist write-back voltage sense amplifier for low voltage-operated SRAMs. - Tahseen Shakir; Manoj Sachdev (SoCC, 2012)

Suppression of on-chip power supply noise generated by a 64-bit static logic ALU block. - Tasreen Charania; Pierce Chuang; Ajoy Opal; Manoj Sachdev (VLSI-SoC, 2012)

A soft error robust 32kb SRAM macro featuring access transistor-less 8T cell in 65-nm. - Jaspal Singh Shah; David Nairn; Manoj Sachdev (VLSI-SoC, 2012)

A Low-Power High-Performance Single-Cycle Tree-Based 64-Bit Binary Comparator. - Pierce Chuang; David Li 002; Manoj Sachdev (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

Performance, Metastability, and Soft-Error Robustness Trade-offs for Flip-Flops in 40 nm CMOS. - David Rennie; David Li 002; Manoj Sachdev; Bharat L. Bhuva; Srikanth Jagannathan; Shi-Jie Wen; Richard Wong (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

A novel voltage-programmed pixel circuit with VT-shift compensation for AMOLED displays. - Maofeng Yang; Nikolas P. Papadopoulos; Czang-Ho Lee; William S. Wong 001; Manoj Sachdev (CICC, 2013)

An Energy-Efficient Offset-Cancelling Sense Amplifier. - Jaspal Singh Shah; David Nairn; Manoj Sachdev (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

Analysis and Design of On-Chip Decoupling Capacitors. - Tasreen Charania; Ajoy Opal; Manoj Sachdev (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Constant Delay Logic Style. - Pierce Chuang; David Li 002; Manoj Sachdev (IEEE Trans. Very Large Scale Integr. Syst., 2013)

A low-leakage, hybrid ESD power supply clamp in 65nm CMOS technology. - Mahdi Elghazali; Manoj Sachdev; Ajoy Opal (CICC, 2014)

A 0.4 V 75 kbit SRAM macro in 28 nm CMOS featuring a 3-adjacent MBU correcting ECC. - Adam Neale; Manoj Sachdev (CICC, 2014)

Embedded tutorial: Test and manufacturability for silicon photonics and 3D integration. - Manoj Sachdev; Tetsuya Iizuka (CICC, 2014)

A hybrid ESD clamp with thyristor delay element and diodes for low-leakage applications. - Mahdi Elghazali; Manoj Sachdev; Ajoy Opal (NEWCAS, 2014)

A body-bias based current sense amplifier for high-speed low-power embedded SRAMs. - Tahseen Shakir; Manoj Sachdev (SoCC, 2014)

A 167-ps 2.34-mW Single-Cycle 64-Bit Binary Tree Comparator With Constant-Delay Logic in 65-nm CMOS. - Pierce I-Jen Chuang; Manoj Sachdev; Vincent C. Gaudet (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

A low energy SRAM-based physically unclonable function primitive in 28 nm CMOS. - Adam Neale; Manoj Sachdev (CICC, 2015)

An FPGA Implementation of a Timing-Error Tolerant Discrete Cosine Transform (Abstract Only). - Yaoqiang Li; Pierce I-Jen Chuang; Andrew A. Kennings; Manoj Sachdev (FPGA, 2015)

Voltage-Boosted Synchronizers. - Yaoqiang Li; Pierce I-Jen Chuang; Andrew A. Kennings; Manoj Sachdev (ACM Great Lakes Symposium on VLSI, 2015)

VLSI implementation of high-throughput, low-energy, configurable MIMO detector. - Pierce I-Jen Chuang; Manoj Sachdev; Vincent C. Gaudet (ICCD, 2015)

A Linear Comparator-Based Fully Digital Delay Element. - Afshin Seraj; Mohammad Maymandi-Nejad; Parvin Bahmanyar; Manoj Sachdev (ISVLSI, 2015)

Runtime slack-deficit detection for a low-voltage DCT circuit. - Yaoqiang Li; Pierce I-Jen Chuang; Andrew A. Kennings; Manoj Sachdev (MWSCAS, 2015)

Adjacent-MBU-Tolerant SEC-DED-TAEC-yAED Codes for Embedded SRAMs. - Adam Neale; Maarten Jonkman; Manoj Sachdev (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Radiation hardened pulsed-latches in 65-nm CMOS. - Jaspal Singh Shah; Manoj Sachdev (CCECE, 2016)

A Low-Leakage, Robust ESD Clamp with Thyristor Delay Element in 65 nm CMOS Technology. - Mahdi Elghazali; Manoj Sachdev; Ajoy Opal (ISVLSI, 2016)

Sense amplifier offset characterisation and test implications for low-voltage SRAMs in 65 nm. - Dhruv Patel 002; Derek Wright; Manoj Sachdev (ETS, 2018)

An ESD transient clamp with 494 pA leakage current in GP 65 nm CMOS technology. - Mahdi Elghazali; Manoj Sachdev; Ajoy Opal (ISQED, 2018)

A 290-mV, 3.34-MHz, 6T SRAM With pMOS Access Transistors and Boosted Wordline in 65-nm CMOS Technology. - Morteza Nabavi; Manoj Sachdev (IEEE J. Solid State Circuits, 2018)

Strengthening PUFs using Composition. - Zhuanhao Wu; Hiren D. Patel; Manoj Sachdev; Mahesh V. Tripunitara (ICCAD, 2019)

A Contention-free, Static, Single-phase Flip-Flop for Low Data Activity Applications. - Ata Khorami; Manoj Sachdev; Mohammad Sharifkhani (SoCC, 2019)

Tutorial 2B: Offset Mitigation in Low-Voltage Sense Amplifiers and Its Implication on SRAM Design and Test. - Manoj Sachdev (SoCC, 2019)

A low-power dynamic comparator for low-offset applications. - Ata Khorami; Roghayeh Saeidi; Manoj Sachdev; Mohammad Sharifkhani (Integr., 2019)

Hybrid Latch-Type Offset Tolerant Sense Amplifier for Low-Voltage SRAMs. - Dhruv Patel 002; Adam Neale; Derek Wright; Manoj Sachdev (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A Parametric DFT Scheme for STT-MRAMs. - Govind Radhakrishnan; Youngki Yoon; Manoj Sachdev (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Realization of an Energy-Efficient, Full-Swing Decoder with Unipolar TFT Technology. - Qing Li 055; Czang-Ho Lee; William S. Wong 001; Manoj Sachdev (CICC, 2020)

Accelerating STT-MRAM Ramp-up Characterization. - Govind Radhakrishnan; Youngki Yoon; Manoj Sachdev (NEWCAS, 2020)

A low-power low-offset charge-sharing technique for double-tail comparators. - Ata Khorami; Roghayeh Saeidi; Manoj Sachdev (Microelectron. J., 2020)

Monitoring Aging Defects in STT-MRAMs. - Govind Radhakrishnan; Youngki Yoon; Manoj Sachdev (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Ultra Low-power, Low-energy Static Single-phase Clocked Flip-flop. - Yugal Kishore Maheshwari; Kleber Stangherlin; Derek Wright; Manoj Sachdev (ICECS, 2021)

Reliable Strong PUF Enrollment and Operation with Temperature and Voltage Optimization. - Kleber Hugo Stangherlin; Manoj Sachdev (ISQED, 2021)

Energy-Efficient Full-Swing Logic Circuits With Unipolar TFTs on Flexible Substrates. - Qing Li 055; Czang-Ho Lee; Mohsen Asad; William S. Wong 001; Manoj Sachdev (IEEE J. Solid State Circuits, 2021)

Body Biased Sense Amplifier With Auto-Offset Mitigation for Low-Voltage SRAMs. - Dhruv Patel 002; Adam Neale; Derek Wright; Manoj Sachdev (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Enhancing Strong PUF Security with Non-monotonic Response Quantization. - Kleber Stangherlin; Zhuanhao Wu; Hiren D. Patel; Manoj Sachdev (CoRR, 2022)

Design Exploration and Security Assessment of PUF-on-PUF Implementations. - Kleber Stangherlin; Zhuanhao Wu; Hiren D. Patel; Manoj Sachdev (CoRR, 2022)

Secure and Lightweight Strong PUF Challenge Obfuscation with Keyed Non-linear FSR. - Kleber Stangherlin; Zhuanhao Wu; Hiren D. Patel; Manoj Sachdev (CoRR, 2022)

Design and Implementation of a Secure RISC-V Microprocessor. - Kleber Stangherlin; Manoj Sachdev (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Testchip Measured CRPs of NMQ strong PUF. - Kleber Stangherlin; Zhuanhao Wu; Hiren D. Patel; Manoj Sachdev (IEEE DataPort, 2022)

Enhancing Strong PUF Security With Nonmonotonic Response Quantization. - Kleber Stangherlin; Zhuanhao Wu; Hiren D. Patel; Manoj Sachdev (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Leveraging Banking and Charge-Sharing schemes for Low-Power Micro-displays. - Shubham Ranjan; Sheida Gohardehi; Manoj Sachdev (CCECE, 2024)

A Low-voltage-Driven Single-ended Column based SRAM for Low-Power Micro-display. - Shubham Ranjan; Sheida Gohardehi; Manoj Sachdev (SOCC, 2024)

A power-efficient, single-phase, contention-free flip-flop with only three clock transistors. - Yugal Kishore Maheshwari; Manoj Sachdev (Microelectron. J., 2024)

Low-Power Row Driver for Digitally Driven OLEDoS Microdisplay. - Sheida Gohardehi; Manoj Sachdev (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Low-Power, Low-Energy, Static, Contention-Free, TSPC Dual-Edge Triggered Flip-Flops. - Yugal Kishore Maheshwari; Manoj Sachdev (IEEE Access, 2025)

VLFF - A very low-power flip-flop with only two clock transistors. - Yugal Kishore Maheshwari; Manoj Sachdev (Integr., 2025)