A RISCy approach to VLSI. - Daniel T. Fitzpatrick; John K. Foderaro; Manolis G. H. Katevenis; Howard A. Landman; David A. Patterson 001; James B. Peek; Zvi Peshkess; Carlo H. Séquin; Robert W. Sherburne; Korbin S. Van Dyke (SIGARCH Comput. Archit. News, 1982)

A Vector Hardware Accelerator with Circuit Simulation Emphasis. - Andrei Vladimirescu; David Weiss; Manolis Katevenis; Zvika Bronstein; Alon Kifir; Karja Danuwidjaja; K. C. Ng; Niraj Jain; Steven Lass (DAC, 1987)

Fast switching and fair control of congested flow in broadband networks. - Manolis Katevenis (IEEE J. Sel. Areas Commun., 1987)

Reducing the Branch Penalty by Rearranging Instructions in Double-Width Memory. - Manolis Katevenis; Nestoras Tzartzanis (ASPLOS, 1991)

Weighted Round-Robin Cell Multiplexing in a General-Purpose ATM Switch Chip. - Manolis Katevenis; Stefanos Sidiropoulos; Costas Courcoubetis (IEEE J. Sel. Areas Commun., 1991)

Pipelined Memory Shared Buffer for VLSI Switches. - Manolis Katevenis; Panagiota Vatsolaki; Aristides Efthymiou (SIGCOMM, 1995)

Telegraphos: High-Performance Networking for Parallel Processing on Workstation Clusters. - Evangelos P. Markatos; Manolis Katevenis (HPCA, 1996)

Pipelined Multi-Queue Management in a VLSI ATM Switch Chip with Credit-Based Flow-Control. - George Kornaros; Christoforos E. Kozyrakis; Panagiota Vatsolaki; Manolis Katevenis (ARVLSI, 1997)

ATLAS: A Single-Chip ATM Switch for NOWs. - Manolis Katevenis; Panagiota Vatsolaki; Dimitrios N. Serpanos; Evangelos P. Markatos (CANPC, 1997)

User-Level DMA without Operating System Kernel Modification. - Evangelos P. Markatos; Manolis Katevenis (HPCA, 1997)

Telegraphos: A Substrate for High-Performance Computing on Workstation Clusters. - Manolis Katevenis; Evangelos P. Markatos; George Kalokerinos; Apostolos Dollas (J. Parallel Distributed Comput., 1997)

The Remote Enqueue Operation on Networks of Workstations. - Evangelos P. Markatos; Manolis Katevenis; Penny Vatsolaki (CANPC, 1998)

Credit-Flow-Controlled ATM for MP Interconnection: The ATLAS I Single-Chip ATM Switch. - Manolis Katevenis; Dimitrios N. Serpanos; Emmanuel Spyridakis (HPCA, 1998)

ATLAS I: a single-chip, gigabit ATM switch with HIC/HS links arid multi-lane back-pressure. - Manolis Katevenis; Dimitrios N. Serpanos; George Dimitriadis (Microprocess. Microsystems, 1998)

Secondary Storage Management for Web Proxies. - Evangelos P. Markatos; Manolis Katevenis; Dionisios N. Pnevmatikatos; Michail Flouris (USENIX Symposium on Internet Technologies and Systems, 1999)

The Remote Enqueue Operation on Networks of Workstations. - Manolis Katevenis; Evangelos P. Markatos; Penny Vatsolaki; Chara Xanthaki (Informatica (Slovenia), 1999)

ATLAS I: implementing a single-chip ATM switch with backpressure. - George Kornaros; Dionisios N. Pnevmatikatos; Panagiota Vatsolaki; George Kalokerinos; Chara Xanthaki; Dimitrios Mavroidis; Dimitrios N. Serpanos; Manolis Katevenis (IEEE Micro, 1999)

Efficient per-flow queueing in DRAM at OC-192 line rate using out-of-order execution techniques. - Aggelos Nikologiannis; Manolis Katevenis (ICC, 2001)

Wormhole IP over (connectionless) ATM. - Manolis Katevenis; Iakovos Mavroidis; Georgios Sapountzis; Evangelia Kalyvianaki; Ioannis Mavroidis; Georgios Glykopoulos (IEEE/ACM Trans. Netw., 2001)

Web-conscious storage management for web proxies. - Evangelos P. Markatos; Dionisios N. Pnevmatikatos; Michail Flouris; Manolis Katevenis (IEEE/ACM Trans. Netw., 2002)

Multiple priorities in a two-lane buffered crossbar. - Nikolaos Chrysos; Manolis Katevenis (GLOBECOM, 2004)

Variable packet size buffered crossbar (CICQ) switches. - Manolis Katevenis; Giorgos Passas; Dimitrios Simos; Ioannis Papaefstathiou; Nikolaos Chrysos (ICC, 2004)

Scheduling in switches with small internal buffers. - Nikolaos Chrysos; Manolis Katevenis (GLOBECOM, 2005)

Variable-size multipacket segments in buffered crossbar (CICQ) architectures. - Manolis Katevenis; Giorgos Passas (ICC, 2005)

Benes switching fabrics with O(N)-complexity internal backpressure. - Georgios Sapountzis; Manolis Katevenis (IEEE Commun. Mag., 2005)

Scheduling in Non-Blocking Buffered Three-Stage Switching Fabrics. - Nikolaos Chrysos; Manolis Katevenis (INFOCOM, 2006)

Approaching Ideal NoC Latency with Pre-Configured Routes. - George Michelogiannakis; Dionisios N. Pnevmatikatos; Manolis Katevenis (NOCS, 2007)

Prototyping Efficient Interprocessor Communication Mechanisms. - Vassilis Papaefstathiou; Dionisios N. Pnevmatikatos; Manolis Marazakis; Giorgos Kalokairinos; Aggelos Ioannou; Michael Papamichael; Stamatis G. Kavadias; Giorgos Mihelogiannakis; Manolis Katevenis (ICSAMOS, 2007)

Pipelined heap (priority queue) management for advanced scheduling in high-speed networks. - Aggelos Ioannou; Manolis Katevenis (IEEE/ACM Trans. Netw., 2007)

Towards unified mechanisms for inter-processor communication. - Manolis Katevenis (ICSAMOS, 2008)

Building an FoC Using Large, Buffered Crossbar Cores. - Dimitrios Simos; Ioannis Papaefstathiou; Manolis Katevenis (IEEE Des. Test Comput., 2008)

FPGA implementation of a configurable cache/scratchpad memory with virtualized user-level RDMA capability. - George Kalokerinos; Vassilis Papaefstathiou; George Nikiforos; Stamatis G. Kavadias; Manolis Katevenis; Dionisios N. Pnevmatikatos; Xiaojun Yang (ICSAMOS, 2009)

End-to-end congestion management for non-blocking multi-stage switching fabrics. - Nikolaos Chrysos; Lydia Y. Chen; Cyriel Minkenberg; Christoforos Kachris; Manolis Katevenis (ANCS, 2010)

On-chip communication and synchronization mechanisms with cache-integrated network interfaces. - Stamatis G. Kavadias; Manolis Katevenis; Michail Zampetakis; Dimitrios S. Nikolopoulos (Conf. Computing Frontiers, 2010)

Efficient implementation of CIOQ switches with sequential iterative matching algorithms. - Xiaojun Yang; Christoforos Kachris; Manolis Katevenis (FPT, 2010)

A 128 x 128 x 24Gb/s Crossbar Interconnecting 128 Tiles in a Single Hop and Occupying 6% of Their Area. - Giorgos Passas; Manolis Katevenis; Dionisios N. Pnevmatikatos (NOCS, 2010)

Network Processing in Multi-core FPGAs with Integrated Cache-Network Interface. - Christoforos Kachris; George Nikiforos; Stamatis G. Kavadias; Vassilis Papaefstathiou; Manolis Katevenis (ReConFig, 2010)

Explicit Communication and Synchronization in SARC. - Manolis Katevenis; Vassilis Papaefstathiou; Stamatis G. Kavadias; Dionisios N. Pnevmatikatos; Federico Silla; Dimitrios S. Nikolopoulos (IEEE Micro, 2010)

Fine-grain OpenMP runtime support with explicit communication hardware primitives. - Pranav Tendulkar; Vassilis Papaefstathiou; George Nikiforos; Stamatis G. Kavadias; Dimitrios S. Nikolopoulos; Manolis Katevenis (DATE, 2011)

An efficient sequential iterative matching algorithm for CIOQ switches. - Yanping Gao; Christoforos Kachris; Manolis Katevenis (ISCC, 2011)

VLSI micro-architectures for high-radix crossbar schedulers. - Giorgos Passas; Manolis Katevenis; Dionisios N. Pnevmatikatos (NOCS, 2011)

Distributed WFQ scheduling converging to weighted max-min fairness. - Nikolaos Chrysos; Manolis Katevenis (Comput. Networks, 2011)

Formic: Cost-efficient and Scalable Prototyping of Manycore Architectures. - Spyros Lyberis; George Kalokerinos; Michalis Lygerakis; Vassilis Papaefstathiou; Dimitrios Tsaliagkos; Manolis Katevenis; Dionisios N. Pnevmatikatos; Dimitrios S. Nikolopoulos (FCCM, 2012)

Cache-Integrated Network Interfaces: Flexible On-Chip Communication and Synchronization for Large-Scale CMPs. - Stamatis G. Kavadias; Manolis Katevenis; Michail Zampetakis; Dimitrios S. Nikolopoulos (Int. J. Parallel Program., 2012)

Crossbar NoCs Are Scalable Beyond 100 Nodes. - Giorgos Passas; Manolis Katevenis; Dionisios N. Pnevmatikatos (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

LP-NUCA: Networks-in-Cache for High-Performance Low-Power Embedded Processors. - Darío Suárez Gracia; Giorgos Dimitrakopoulos; Teresa Monreal Arnal; Manolis Katevenis; Víctor Viñals Yúfera (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Prefetching and cache management using task lifetimes. - Vassilis Papaefstathiou; Manolis Katevenis; Dimitrios S. Nikolopoulos; Dionisios N. Pnevmatikatos (ICS, 2013)

NP-SARC: Scalable network processing in the SARC multi-core FPGA platform. - Christoforos Kachris; George Nikiforos; Vassilis Papaefstathiou; Stamatis G. Kavadias; Manolis Katevenis (J. Syst. Archit., 2013)

EUROSERVER: Energy Efficient Node for European Micro-Servers. - Yves Durand; Paul M. Carpenter; Stefano Adami; Angelos Bilas; Denis Dutoit; Alexis Farcy; Georgi Gaydadjiev; John Goodacre; Manolis Katevenis; Manolis Marazakis; Emil Matús; Iakovos Mavroidis; et al. (DSD, 2014)

Design trade-offs in energy efficient NoC architectures. - Antonis Psathakis; Vassilis Papaefstathiou; Manolis Katevenis; Dionisios N. Pnevmatikatos (NOCS, 2014)

Design space exploration for fair resource-allocated NoC architectures. - Antonis Psathakis; Vassilis Papaefstathiou; Manolis Katevenis; Dionisios N. Pnevmatikatos (ICSAMOS, 2014)

FPGA prototyping of emerging manycore architectures for parallel programming research using Formic boards. - Spyros Lyberis; George Kalokerinos; Michalis Lygerakis; Vassilis Papaefstathiou; Iakovos Mavroidis; Manolis Katevenis; Dionisios N. Pnevmatikatos; Dimitrios S. Nikolopoulos (J. Syst. Archit., 2014)

A Systematic Evaluation of Emerging Mesh-like CMP NoCs. - Antonis Psathakis; Vassilis Papaefstathiou; Nikolaos Chrysos; Fabien Chaix; Evangelos Vasilakis; Dionisios N. Pnevmatikatos; Manolis Katevenis (ANCS, 2015)

The Combined Input-Output Queued Crossbar Architecture for High-Radix On-Chip Switches. - Giorgos Passas; Manolis Katevenis; Dionisios N. Pnevmatikatos (IEEE Micro, 2015)

The ExaNeSt Project: Interconnects, Storage, and Packaging for Exascale Systems. - Manolis Katevenis; Nikolaos Chrysos; Manolis Marazakis; Iakovos Mavroidis; Fabien Chaix; Nikolaos D. Kallimanis; Javier Navaridas; John Goodacre; Piero Vicini; Andrea Biagioni; Pier Stanislao Paolucci; Alessandro Lonardo; et al. (DSD, 2016)

Discharging the Network From Its Flow Control Headaches: Packet Drops and HOL Blocking. - Nikolaos Chrysos; Lydia Y. Chen; Christoforos Kachris; Manolis Katevenis (IEEE/ACM Trans. Netw., 2016)

The Next Generation of Exascale-Class Systems: The ExaNeSt Project. - Roberto Ammendola; Andrea Biagioni; Paolo Cretaro; Ottorino Frezza; Francesca Lo Cicero; Alessandro Lonardo; Michele Martinelli; Pier Stanislao Paolucci; Elena Pastorelli; Francesco Simula; Piero Vicini; Giuliano Taffoni; et al. (DSD, 2017)

Modeling energy-performance tradeoffs in ARM big.LITTLE architectures. - Evangelos Vasilakis; Ioannis Sourdis; Vassilis Papaefstathiou; Antonis Psathakis; Manolis G. H. Katevenis (PATMOS, 2017)

Accurate Congestion Control for RDMA Transfers. - Dimitris Giannopoulos; Nikos Chrysos; Evangelos Mageiropoulos; Giannis Vardas; Leandros Tzanakis; Manolis Katevenis (NOCS, 2018)

Next generation of Exascale-class systems: ExaNeSt project and the status of its interconnect and storage development. - Manolis Katevenis; Roberto Ammendola; Andrea Biagioni; Paolo Cretaro; Ottorino Frezza; Francesca Lo Cicero; Alessandro Lonardo; Michele Martinelli; Pier Stanislao Paolucci; Elena Pastorelli; Francesco Simula; Piero Vicini; et al. (Microprocess. Microsystems, 2018)

Towards Exascale: Measuring the Energy Footprint of Astrophysics HPC Simulations. - Giuliano Taffoni; Manolis Katevenis; Renato Panchieri; Gino Perna; Luca Tornatore; David Goz; Antonio Ragagnin; Sara Bertocco; Igor Coretti; Manolis Marazakis; Fabien Chaix; Manolis Ploumidis (eScience, 2019)

Efficient Convolutional Neural Network Weight Compression for Space Data Classification on Multi-fpga Platforms. - George Pitsis; Grigorios Tsagkatakis; Christos Kozanitis; Ioannis Kalomoiris; Aggelos Ioannou; Apostolos Dollas; Manolis G. H. Katevenis; Panagiotis Tsakalides (ICASSP, 2019)

Implementation and Impact of an Ultra-Compact Multi-FPGA Board for Large System Prototyping. - Fabien Chaix; Georgios Ailamakis; Theocharis Vavouris; Astrinos Damianakis; Manolis Katevenis; Iakovos Mavroidis; Aggelos Ioannou; Nikolaos Kossifidis; Nikolaos Dimou; Giorgos Ieronymakis; Manolis Marazakis; Vassilis Papaefstathiou; et al. (H2RC@SC, 2019)

Software and Hardware Co-design for Low-Power HPC Platforms. - Manolis Ploumidis; Nikolaos D. Kallimanis; Marios Asiminakis; Nikos Chrysos; Pantelis Xirouchakis; Michalis Gianoudis; Leandros Tzanakis; Nikolaos Dimou; Antonis Psistakis; Panagiotis Peristerakis; Giorgos Kalokairinos; Vassilis Papaefstathiou; et al. (ISC Workshops, 2019)

Shall numerical astrophysics step into the era of Exascale computing? - Giuliano Taffoni; Giuseppe Murante; Luca Tornatore; David Goz; Stefano Borgani; Manolis Katevenis; Nikolaos Chrysos; Manolis Marazakis (CoRR, 2019)

Prototyping a Configurable Cache/Scratchpad Memory with Virtualized User-Level RDMA Capability. - George Kalokerinos; Vassilis Papaefstathiou; George Nikiforos; Stamatis G. Kavadias; Xiaojun Yang; Dionisios N. Pnevmatikatos; Manolis Katevenis (Trans. High Perform. Embed. Archit. Compil., 2019)

PART: Pinning Avoidance in RDMA Technologies. - Antonis Psistakis; Nikos Chrysos; Fabien Chaix; Marios Asiminakis; Michalis Giannioudis; Pantelis Xirouchakis; Vassilis Papaefstathiou; Manolis Katevenis (NOCS, 2020)

Using hls4ml to Map Convolutional Neural Networks on Interconnected FPGA Devices. - Evangelos Mageiropoulos; Nikolaos Chrysos; Nikolaos Dimou; Manolis Katevenis (FCCM, 2021)

RED-SEA: Network Solution for Exascale Architectures. - Andrea Biagioni; Paolo Cretaro; Ottorino Frezza; Francesca Lo Cicero; Alessandro Lonardo; Michele Martinelli; Pier Stanislao Paolucci; Elena Pastorelli; Francesco Simula; Matteo Turisini; Piero Vicini; Roberto Ammendola; et al. (DSD, 2022)

Optimized Page Fault Handling During RDMA. - Antonis Psistakis; Nikos Chrysos; Fabien Chaix; Marios Asiminakis; Michalis Gianioudis; Pantelis Xirouchakis; Vassilis Papaefstathiou; Manolis Katevenis (IEEE Trans. Parallel Distributed Syst., 2022)

The ExaNeSt Prototype: Evaluation of Efficient HPC Communication Hardware in an ARM-based Multi-FPGA Rack. - Manolis Ploumidis; Fabien Chaix; Nikolaos Chrysos; Marios Asiminakis; Vassilis Flouris; Nikolaos D. Kallimanis; Nikolaos Kossifidis; Michael Nikoloudakis; Polydoros Petrakis; Nikolaos Dimou; Michalis Gianioudis; Georgios Ieronymakis; et al. (CoRR, 2023)

Low-latency Communication in RISC-V Clusters. - Michalis Gianioudis; Pantelis Xirouchakis; Charisios Loukas; Evangelos Mageiropoulos; Orestis Mousouros; Sokratis Mpartzis; Aggelos Ioannou; Vassilis Papaefstathiou; Manolis Katevenis; Nikolaos Chrysos (HPC Asia, 2024)

RED-SEA Project: Towards a new-generation European interconnect. - María Engracia Gómez; Julio Sahuquillo; Andrea Biagioni; Nikos Chrysos; Damien Berton; Ottorino Frezza; Francesca Lo Cicero; Alessandro Lonardo; Michele Martinelli; Pier Stanislao Paolucci; Elena Pastorelli; Francesco Simula; et al. (Microprocess. Microsystems, 2024)

The ExaNeSt Prototype: Evaluation of Efficient HPC Communication Hardware in an ARM-based Multi-FPGA Rack. - Manolis Ploumidis; Fabien Chaix; Nikolaos Chrysos; Marios Assiminakis; Nikolaos D. Kallimanis; Nikolaos Kossifidis; Michael Nikoloudakis; Nikolaos Dimou; Michalis Gianioudis; George Ieronymakis; Aggelos Ioannou; George Kalokerinos; et al. (ACM Trans. Reconfigurable Technol. Syst., 2025)