An Improved Conversion Circuit for Redundant Binary to Conventional Binary Representation. - Snigdha Subhadarshinee Tripathy; Ranjan Kumar Barik; Manoranjan Pradhan (CICBA (1), 2017)

Efficient ASIC and FPGA implementation of cube architecture. - Ranjan Kumar Barik; Manoranjan Pradhan (IET Comput. Digit. Tech., 2017)

Efficient Conversion Technique from Redundant Binary to NonRedundant Binary Representation. - Ranjan Kumar Barik; Manoranjan Pradhan; Rutuparna Panda (J. Circuits Syst. Comput., 2017)

An efficient redundant binary adder with revised computational rules. - Ranjan Kumar Barik; Bandan Kumar Bhoi; Manoranjan Pradhan (Comput. Electr. Eng., 2018)

Fast signed multiplier using Vedic Nikhilam algorithm. - Satya Ranjan Sahu; Bandan Kumar Bhoi; Manoranjan Pradhan (IET Circuits Devices Syst., 2020)

Improved Redundant Binary Adder Realization in FPGA. - Satya Ranjan Sahu; Bandan Kumar Bhoi; Manoranjan Pradhan (J. Circuits Syst. Comput., 2021)

Design and Analysis of Area and Time Efficient Signed Square Architecture Using Nonconventional Method. - Niharika Behera; Manoranjan Pradhan; Bandan Kumar Bhoi (J. Circuits Syst. Comput., 2025)