Design exploration of a NVM based hybrid instruction memory organization for embedded platforms. - Manu Perumkunnil Komalan; José Ignacio Gómez Pérez; Christian Tenllado; José Miguel Montañana; Antonio Artés; José Francisco Tirado Fernández; Francky Catthoor (Des. Autom. Embed. Syst., 2013)

Feasibility exploration of NVM based I-cache through MSHR enhancements. - Manu Komalan; José Ignacio Gómez Pérez; Christian Tenllado; Praveen Raghavan; Matthias Hartmann; Francky Catthoor (DATE, 2014)

System level exploration of a STT-MRAM based level 1 data-cache. - Manu Perumkunnil Komalan; Christian Tenllado; José Ignacio Gómez Pérez; Francisco Tirado Fernández; Francky Catthoor (DATE, 2015)

Cross-layer design and analysis of a low power, high density STT-MRAM for embedded systems. - Manu Komalan; Sushil Sakhare; Trong Huynh Bao; Siddharth Rao; Woojin Kim; Christian Tenllado; José Ignacio Gómez; Gouri Sankar Kar; Arnaud Furnémont; Francky Catthoor (ISCAS, 2017)

System Level Management of Hybrid Memory Systems ; Systeem niveau beheer van hybride geheugen systemen ; Gestión de jerarquías de memoria híbridas a nivel de sistema. - Manu Perumkunnil Komalan (2017)

Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks. - Manu Komalan; Oh Hyung Rock; Matthias Hartmann; Sushil Sakhare; Christian Tenllado; José Ignacio Gómez; Gouri Sankar Kar; Arnaud Furnémont; Francky Catthoor; Sophiane Senni; David Novo; Abdoulaye Gamatié; et al. (DATE, 2018)

Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications. - Trong Huynh Bao; Anabela Veloso; Sushil Sakhare; Philippe Matagne; Julien Ryckaert; Manu Perumkunnil; Davide Crotti; Farrukh Yasin; Alessio Spessot; Arnaud Furnémont; Gouri Sankar Kar; Anda Mocuta (DAC, 2019)

A Comparative Analysis on the Impact of Bank Contention in STT-MRAM and SRAM Based LLCs. - Timon Evenblij; Christian Tenllado; Manu Perumkunnil; Francky Catthoor; Sushil Sakhare; Peter Debacker; Gouri Sankar Kar; Arnaud Furnémont; Nicolas Bueno; José Ignacio Gómez Pérez (ICCD, 2019)

Heterogeneous 3D Integration for a RISC-V System With STT-MRAM. - Lingjun Zhu; Lennart Bamberg; Anthony Agnesina; Francky Catthoor; Dragomir Milojevic; Manu Komalan; Julien Ryckaert; Alberto García-Ortiz; Sung Kyu Lim (IEEE Comput. Archit. Lett., 2020)

Memory Hierarchy Calibration Based on Real Hardware In-order Cores for Accurate Simulation. - Quentin Huppert; Timon Evenblij; Manu Perumkunnil; Francky Catthoor; Lionel Torres; David Novo (DATE, 2021)

Enhanced data integrity of In-Ga-Zn-Oxide based Capacitor-less 2T memory for DRAM applications. - Hyungrock Oh; Attilio Belmonte; Manu Perumkunnil; Jérôme Mitard; Nouredine Rassoul; Gabriele Luca Donadio; Romain Delhougne; Arnaud Furnémont; Gouri Sankar Kar; Wim Dehaene (ESSDERC, 2021)

STT-MRAM array performance improvement through optimization of Ion Beam Etch and MTJ for Last-Level Cache application. - Sidharth Rao; Woojin Kim; Simon Van Beek; Shreya Kundu; Manu Perumkunnil; Stefan Cosemans; Farrukh Yasin; Sebastien Couet; Robert Carpenter; Barry J. O'Sullivan; Shamin H. Sharifi; N. Jossart; et al. (IMW, 2021)

Power, Performance, Area and Cost Analysis of Memory-on-Logic Face-to-Face Bonded 3D Processor Designs. - Anthony Agnesina; Moritz Brunion; Jinwoo Kim; Alberto García Ortiz; Dragomir Milojevic; Francky Catthoor; Manu Perumkunnil; Sung Kyu Lim (ISLPED, 2021)

High-Performance Logic-on-Memory Monolithic 3-D IC Designs for Arm Cortex-A Processors. - Lingjun Zhu; Lennart Bamberg; Sai Surya Kiran Pentapati; Kyungwook Chang; Francky Catthoor; Dragomir Milojevic; Manu Komalan; Brian Cline; Saurabh Sinha; Xiaoqing Xu; Alberto García-Ortiz; Sung Kyu Lim (IEEE Trans. Very Large Scale Integr. Syst., 2021)

CIM-based Robust Logic Accelerator using 28 nm STT-MRAM Characterization Chip Tape-out. - Abhairaj Singh; Mahdi Zahedi; Taha Shahroodi; Mohit Gupta 004; Anteneh Gebregiorgis; Manu Komalan; Rajiv V. Joshi; Francky Catthoor; Rajendra Bishnoi; Said Hamdioui (AICAS, 2022)

Design exploration of IGZO diode based VCMA array design for Storage Class Memory Applications. - Mohit Gupta 004; Manu Perumkunnil; Andrea Fantini; Saeideh Alinezhad Chamazcoti; Woojin Kim; Marie Garcia Bardon; Gouri Sankar Kar; Arnaud Furnémont (ESSDERC, 2022)

Hier-3D: A Hierarchical Physical Design Methodology for Face-to-Face-Bonded 3D ICs. - Anthony Agnesina; Moritz Brunion; Alberto García Ortiz; Francky Catthoor; Dragomir Milojevic; Manu Komalan; Matheus A. Cavalcante; Samuel Riedel; Luca Benini; Sung Kyu Lim (ISLPED, 2022)

Analyzing the Electromigration Challenges of Computation in Resistive Memories. - Mahta Mayahinia; Mehdi B. Tahoori; Manu Perumkunnil; Kristof Croes; Francky Catthoor (ITC, 2022)

Time-Dependent Electromigration Modeling for Workload-Aware Design-Space Exploration in STT-MRAM. - Mahta Mayahinia; Mehdi B. Tahoori; Manu Perumkunnil Komalan; Houman Zahedmanesh; Kristof Croes; Tommaso Marinelli; José Ignacio Gómez Pérez; Timon Evenblij; Gouri Sankar Kar; Francky Catthoor (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Microarchitectural Exploration of STT-MRAM Last-level Cache Parameters for Energy-efficient Devices. - Tommaso Marinelli; José Ignacio Gómez Pérez; Christian Tenllado; Manu Komalan; Mohit Gupta 004; Francky Catthoor (ACM Trans. Embed. Comput. Syst., 2022)

STT-MRAM Stochastic and Defects-aware DTCO for Last Level Cache at Advanced Process Nodes. - Fernando García-Redondo; S. Rao; M. Gupta; Manu Perumkunnil; Y. Xiang; D. Abdi; Simon Van Beek; S. Couet; Marie Garcia Bardon (ESSDERC, 2023)

Design Technology co-optimization of 1D-1VCMA to improve read performance for SCM applications. - Mohit Kumar Gupta 001; Manu Perumkunnil; Dwaipayan Biswas; Saeideh Alinezhad Chamazcoti; Gouri Sankar Kar; Arnaud Furnémont; Julien Ryckaert (ISCAS, 2023)

Impact of interconnects enhancement on SRAM design beyond 5nm technology node. - Mohit Kumar Gupta 001; Pieter Weckx; Manu Perumkunnil Komalan; Julien Ryckaert (ISCAS, 2023)

AMPeD: An Analytical Model for Performance in Distributed Training of Transformers. - Diksha Moolchandani; Joyjit Kundu; Frederik Ruelens; Peter Vrancx; Timon Evenblij; Manu Perumkunnil (ISPASS, 2023)

Beyond RSS: Towards Intelligent Dynamic Memory Management (Work in Progress). - Christos Panagiotis Lamprakos; Sotirios Xydis; Peter Kourzanov; Manu Perumkunnil; Francky Catthoor; Dimitrios Soudris (MPLR, 2023)

Exploring Pareto-Optimal Hybrid Main Memory Configurations Using Different Emerging Memories. - Saeideh Alinezhad Chamazcoti; Mohit Gupta 004; Hyungrock Oh; Timon Evenblij; Francky Catthoor; Manu Perumkunnil Komalan; Gouri Sankar Kar; Arnaud Furnémont (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Hier-3D: A Methodology for Physical Hierarchy Exploration of 3-D ICs. - Nesara Eranna Bethur; Anthony Agnesina; Moritz Brunion; Alberto García Ortiz; Francky Catthoor; Dragomir Milojevic; Manu Komalan; Matheus A. Cavalcante; Samuel Riedel; Luca Benini; Sung Kyu Lim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

A System Level Performance Evaluation for Superconducting Digital Systems. - Joyjit Kundu; Debjyoti Bhattacharjee; Nathan Josephsen; Ankit Pokhrel; Udara De Silva; Wenzhe Guo; Steven Van Winckel; Steven Brebels; Quentin Herr; Anna Herr; Manu Perumkunnil (DATE, 2025)

ARC: Application-Level Refinement and Cache Mapping for Performance Optimization on the Edge. - Manolis Katsaragakis; Christos P. Lamprakos; Peter Kourzanov; Manu Perumkunnil Komalan; Lazaros Papadopoulos; Francky Catthoor; Dimitrios Soudris (ISCAS, 2025)

System-performance and cost modeling of Large Language Model training and inference. - Wenzhe Guo; Joyjit Kundu; Uras Tos; Weijiang Kong; Giuliano Sisto; Timon Evenblij; Manu Perumkunnil (CoRR, 2025)