An accurate functional level concurrent fault simulator. - Manuel A. d'Abreu; Edward W. Thompson (DAC, 1980)

Oracle - a simulator for Bipolar and MOS IC design. - Manuel A. d'Abreu; K. L. Cheong; C. T. Flanagan (DAC, 1984)

Analog Compilation Based on Successive Decompositions. - E. Berkcan; Manuel A. d'Abreu; W. Laughton (DAC, 1988)

Constrained conditional resource sharing in pipeline synthesis. - Ki Soo Hwang; Albert E. Casavant; Martin Dragomirecky; Manuel A. d'Abreu (ICCAD, 1988)

Flexible module generation in the FACE design environment. - William D. Smith; Jeffrey R. Jasica; Michael J. Hartman; Manuel A. d'Abreu (ICCAD, 1988)

High-Level Graphical User Interface Management in the FACE Synthesis Environment. - Martin Dragomirecky; Ephraim P. Glinert; Jeffrey R. Jasica; David A. Duff; William D. Smith; Manuel A. d'Abreu (DAC, 1989)

FACE Core Environment: The Model and Its Application in CAE/CAD Tool Development. - William D. Smith; David A. Duff; Martin Dragomirecky; James L. Caldwell; Michael J. Hartman; Jeffrey R. Jasica; Manuel A. d'Abreu (DAC, 1989)

Scheduling and hardware sharing in pipelined data paths. - Ki Soo Hwang; Albert E. Casavant; Ching-Tang Chang; Manuel A. d'Abreu (ICCAD, 1989)

A synthesis environment for designing DSP systems. - Albert E. Casavant; Manuel A. d'Abreu; Martin Dragomirecky; David A. Duff; Jeffrey R. Jasica; Michael J. Hartman; Ki Soo Hwang; William D. Smith (IEEE Des. Test, 1989)

Concurrent Error Detection and Fault-Tolerance in Linear Digital State Variable Systems. - Abhijit Chatterjee; Manuel A. d'Abreu (FTCS, 1991)

Syndrome-Based Functional Delay Fault Location in Linear Digital Data-Flow Graphs. - Abhijit Chatterjee; Manuel A. d'Abreu (ICCD, 1991)

Automatic test generation for linear digital systems with bi-level search using matrix transform methods. - Rabindra K. Roy; Abhijit Chatterjee; Janak H. Patel; Jacob A. Abraham; Manuel A. d'Abreu (ICCAD, 1992)

Delay fault testing of iterative arithmetic arrays. - Rabindra K. Roy; Naveena Nagi; Abhijit Chatterjee; Manuel A. d'Abreu (VTS, 1992)

Greedy Hardware Optimization for Linear Digital Systems Using Number Splitting. - Abhijit Chatterjee; Rabindra K. Roy; Manuel A. d'Abreu (VLSI Design, 1993)

The Design of Fault-Tolerant Linear Digital State Variable Systems: Theory and Techniques. - Abhijit Chatterjee; Manuel A. d'Abreu (IEEE Trans. Computers, 1993)

Greedy hardware optimization for linear digital circuits using number splitting and refactorization. - Abhijit Chatterjee; Rabindra K. Roy; Manuel A. d'Abreu (IEEE Trans. Very Large Scale Integr. Syst., 1993)

Microprocessor Testing: Which Technique is Best? (Panel). - Jacob A. Abraham; Sandip Kundu; Janak H. Patel; Manuel A. d'Abreu; Bulent I. Dervisoglu; Marc E. Levitt; Hector R. Sucar; Ron G. Walther (DAC, 1994)

A Hierarchal Approach for Power Reduction in VLSI Chips. - Prakash Arunachalam; Jacob A. Abraham; Manuel A. d'Abreu (Great Lakes Symposium on VLSI, 1996)

Distributed Mixed Level Logic and Fault Simulation on the Pentium® Pro Microprocessor. - Sankaran Karthik; Mark Aitken; Glidden Martin; Srinivasu Pappula; Bob Stettler; Praveen Vishakantaiah; Manuel A. d'Abreu; Jacob A. Abraham (ITC, 1996)

FzCRITIC - A Functional Timing Verifier Using a Novel Fuzzy Delay Model. - Rathish Jayabharathi; Manuel A. d'Abreu; Jacob A. Abraham (VLSI Design, 1999)

Manufacturing and Test Considerations in System-On-Chip Designs. - Manuel A. d'Abreu (VLSI Design, 2000)

Noise-Its Sources, and Impact on Design and Test of Mixed Signal Circuits. - Manuel A. d'Abreu (DELTA, 2002)

Tri-Scan: A Novel DFT Technique for CMOS Path Delay Fault Testing. - Ramyanshu Datta; Ravi Gupta; Antony Sebastine; Jacob A. Abraham; Manuel A. d'Abreu (ITC, 2004)

Panel: SoC power management implications on validation and testing. - Bhanu Kapoor; John Goodenough 001; Shankar Hemmady; Shireesh Verma; Manuel A. d'Abreu; Kaushik Roy 001 (HLDVT, 2008)

Controllability of Static CMOS Circuits for Timing Characterization. - Ramyanshu Datta; Ravi Gupta; Antony Sebastine; Jacob A. Abraham; Manuel A. d'Abreu (J. Electron. Test., 2008)

Impact of SoC power management techniques on verification and testing. - Bhanu Kapoor; Shankar Hemmady; Shireesh Verma; Kaushik Roy 001; Manuel A. d'Abreu (ISQED, 2009)

Nand Flash Memory - Product Trends, Technology Overview, and Technical Challenges. - Manuel A. d'Abreu (Asian Test Symposium, 2011)