An Evaluation of Parallel Computing in PC Clusters with Fast Ethernet. - Manuel E. Acacio; Óscar Cánovas Reverte; José M. García 001; Pedro E. López-de-Teruel (ACPC, 1999)

P-EDR: An Algorithm for Parallel Implementation of Parzen Density Estimation from Uncertain Observations. - Pedro E. López-de-Teruel; José M. García 001; Manuel E. Acacio; Óscar Cánovas Reverte (IPPS/SPDP, 1999)

A Performance Evaluation of P-EDR in Different Parallel Environments. - Manuel E. Acacio; José M. García 001; Pedro E. López-de-Teruel (PDPTA, 1999)

The MPI-Delphi Interface: A Visual Programming Environment for Clusters of Workstations. - Manuel E. Acacio; Pedro E. López-de-Teruel; José M. García 001; Óscar Cánovas Reverte (PDPTA, 1999)

The Parallel EM Algorithm and its Applications in Computer Vision. - Pedro E. López-de-Teruel; José M. García 001; Manuel E. Acacio (PDPTA, 1999)

A New Scalable Directory Architecture for Large-Scale Multiprocessors. - Manuel E. Acacio; José González 002; José M. García 001; José Duato (HPCA, 2001)

The Use of Prediction for Accelerating Upgrade Misses in cc-NUMA Multiprocessors. - Manuel E. Acacio; José González 002; José M. García 001; José Duato (IEEE PACT, 2002)

A Novel Approach to Reduce L2 Miss Latency in Shared-Memory Multiprocessors. - Manuel E. Acacio; José González 002; José M. García 001; José Duato (IPDPS, 2002)

Reducing the Latency of L2 Misses in Shared-Memory Multiprocessors through On-Chip Directory Integration. - Manuel E. Acacio; José González 002; José M. García 001; José Duato (PDP, 2002)

Owner prediction for accelerating cache-to-cache transfer misses in a cc-NUMA architecture. - Manuel E. Acacio; José González 002; José M. García 001; José Duato (SC, 2002)

MPI-Delphi: an MPI implementation for visual programming environments and heterogeneous computing. - Manuel E. Acacio; Óscar Cánovas Reverte; José M. García 001; Pedro E. López-de-Teruel (Future Gener. Comput. Syst., 2002)

On the Evaluation of x86 Web Servers Using Simics: Limitations and Trade-Offs. - Francisco J. Villa; Manuel E. Acacio; José M. García 001 (International Conference on Computational Science, 2004)

An Architecture for High-Performance Scalable Shared-Memory Multiprocessors Exploiting On-Chip Integration. - Manuel E. Acacio; José González 002; José M. García 001; José Duato (IEEE Trans. Parallel Distributed Syst., 2004)

A Novel Lightweight Directory Architecture for Scalable Shared-Memory Multiprocessors. - Alberto Ros 001; Manuel E. Acacio; José M. García 001 (Euro-Par, 2005)

Memory Subsystem Characterization in a 16-Core Snoop-Based Chip-Multiprocessor Architecture. - Francisco J. Villa; Manuel E. Acacio; José M. García 001 (HPCC, 2005)

Optimizing a 3D-FWT Video Encoder for SMPs and HyperThreading Architectures. - Ricardo Fernández-Pascual; José M. García 001; Gregorio Bernabé; Manuel E. Acacio (PDP, 2005)

Evaluating IA-32 web servers through simics: a practical experience. - Francisco J. Villa; Manuel E. Acacio; José M. García 001 (J. Syst. Archit., 2005)

A Two-Level Directory Architecture for Highly Scalable cc-NUMA Multiprocessors. - Manuel E. Acacio; José González 002; José M. García 001; José Duato (IEEE Trans. Parallel Distributed Syst., 2005)

An efficient cache design for scalable glueless shared-memory multiprocessors. - Alberto Ros 001; Manuel E. Acacio; José M. García 001 (Conf. Computing Frontiers, 2006)

On the Evaluation of Dense Chip-Multiprocessor Architectures. - Francisco J. Villa; Manuel E. Acacio; José M. García 001 (ICSAMOS, 2006)

Sim-PowerCMP: A Detailed Simulator for Energy Consumption Analysis in Future Embedded CMP Architectures. - Antonio Flores; Juan L. Aragón; Manuel E. Acacio (AINA Workshops (1), 2007)

Efficient Message Management in Tiled CMP Architectures Using a Heterogeneous Interconnection Network. - Antonio Flores; Juan L. Aragón; Manuel E. Acacio (HiPC, 2007)

Direct Coherence: Bringing Together Performance and Scalability in Shared-Memory Multiprocessors. - Alberto Ros 001; Manuel E. Acacio; José M. García 001 (HiPC, 2007)

A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures. - Ricardo Fernández-Pascual; José M. García 001; Manuel E. Acacio; José Duato (HPCA, 2007)

An efficient implementation of a 3D wavelet transform based encoder on hyper-threading technology. - Gregorio Bernabé; Ricardo Fernández-Pascual; José M. García 001; Manuel E. Acacio; José González 002 (Parallel Comput., 2007)

Scalable Directory Organization for Tiled CMP Architectures. - Alberto Ros 001; Manuel E. Acacio; José M. García 001 (CDES, 2008)

Multicore Platforms for Scientific Computing: Cell BE and NVIDIA Tesla. - Juan Fernández 001; Manuel E. Acacio; Gregorio Bernabé; José L. Abellán; Joaquín Franco (CSC, 2008)

A fault-tolerant directory-based cache coherence protocol for CMP architectures. - Ricardo Fernández-Pascual; José M. García 001; Manuel E. Acacio; José Duato (DSN, 2008)

Fault-Tolerant Cache Coherence Protocols for CMPs: Evaluation and Trade-Offs. - Ricardo Fernández-Pascual; José M. García 001; Manuel E. Acacio; José Duato (HiPC, 2008)

Directory-Based Conflict Detection in Hardware Transactional Memory. - J. Rubén Titos Gil; Manuel E. Acacio; José M. García 001 (HiPC, 2008)

Characterizing the Basic Synchronization and Communication Operations in Dual Cell-Based Blades. - José L. Abellán; Juan Fernández 001; Manuel E. Acacio (ICCS (1), 2008)

Address Compression and Heterogeneous Interconnects for Energy-Efficient High-Performance in Tiled CMPs. - Antonio Flores; Manuel E. Acacio; Juan L. Aragón (ICPP, 2008)

DiCo-CMP: Efficient cache coherency in tiled CMP architectures. - Alberto Ros 001; Manuel E. Acacio; José M. García 001 (IPDPS, 2008)

CellStats: A Tool to Evaluate the Basic Synchronization and Communication Operations of the Cell BE. - José L. Abellán; Juan Fernández 001; Manuel E. Acacio (PDP, 2008)

Characterization of Conflicts in Log-Based Transactional Memory (LogTM). - J. Rubén Titos Gil; Manuel E. Acacio; José Manuel García Carrasco (PDP, 2008)

Two proposals for the inclusion of directory information in the last-level private caches of glueless shared-memory multiprocessors. - Alberto Ros 001; Ricardo Fernández-Pascual; Manuel E. Acacio; José M. García 001 (J. Parallel Distributed Comput., 2008)

An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures. - Antonio Flores; Juan L. Aragón; Manuel E. Acacio (J. Supercomput., 2008)

Extending the TokenCMP Cache Coherence Protocol for Low Overhead Fault Tolerance in CMP Architectures. - Ricardo Fernández-Pascual; José M. García 001; Manuel E. Acacio; José Duato (IEEE Trans. Parallel Distributed Syst., 2008)

Dealing with Traffic-Area Trade-Off in Direct Coherence Protocols for Many-Core CMPs. - Alberto Ros 001; Manuel E. Acacio; José M. García 001 (APPT, 2009)

Fast and Efficient Synchronization and Communication Collective Primitives for Dual Cell-Based Blades. - Epifanio Gaona-Ramírez; Juan Fernández 001; Manuel E. Acacio (Euro-Par, 2009)

Distance-aware round-robin mapping for large NUCA caches. - Alberto Ros 001; Marcelo Cintra; Manuel E. Acacio; José M. García 001 (HiPC, 2009)

Speculation-based conflict resolution in hardware transactional memory. - J. Rubén Titos Gil; Manuel E. Acacio; José Manuel García Carrasco (IPDPS, 2009)

A Parallel Implementation of the 2D Wavelet Transform Using CUDA. - Joaquín Franco; Gregorio Bernabé; Juan Fernández 001; Manuel E. Acacio (PDP, 2009)

Efficient and scalable barrier synchronization for many-core CMPs. - José L. Abellán; Juan Fernández 001; Manuel E. Acacio (Conf. Computing Frontiers, 2010)

Evaluation of Low-Overhead Organizations for the Directory in Future Many-Core CMPs. - Alberto Ros 001; Manuel E. Acacio (Euro-Par Workshops, 2010)

EMC2: Extending Magny-Cours coherence for large-scale servers. - Alberto Ros 001; Blas Cuesta; Ricardo Fernández-Pascual; María Engracia Gómez; Manuel E. Acacio; Antonio Robles; José M. García 001; José Duato (HiPC, 2010)

A G-Line-Based Network for Fast and Efficient Barrier Synchronization in Many-Core CMPs. - José L. Abellán; Juan Fernández 001; Manuel E. Acacio (ICPP, 2010)

Energy-Efficient Hardware Prefetching for CMPs Using Heterogeneous Interconnects. - Antonio Flores; Juan L. Aragón; Manuel E. Acacio (PDP, 2010)

Characterizing Energy Consumption in Hardware Transactional Memory Systems. - Epifanio Gaona-Ramírez; J. Rubén Titos Gil; Juan Fernández 001; Manuel E. Acacio (SBAC-PAD, 2010)

Exploiting address compression and heterogeneous interconnects for efficient message management in tiled CMPs. - Antonio Flores; Manuel E. Acacio; Juan L. Aragón (J. Syst. Archit., 2010)

A scalable organization for distributed directories. - Alberto Ros 001; Manuel E. Acacio; José M. García 001 (J. Syst. Archit., 2010)

Heterogeneous Interconnects for Energy-Efficient Message Management in CMPs. - Antonio Flores; Juan L. Aragón; Manuel E. Acacio (IEEE Trans. Computers, 2010)

Characterizing the basic synchronization and communication operations in Dual Cell-based Blades through CellStats. - José L. Abellán; Juan Fernández 001; Manuel E. Acacio (J. Supercomput., 2010)

Dealing with Transient Faults in the Interconnection Network of CMPs at the Cache Coherence Level. - Ricardo Fernández-Pascual; José M. García 001; Manuel E. Acacio; José Duato (IEEE Trans. Parallel Distributed Syst., 2010)

A Direct Coherence Protocol for Many-Core Chip Multiprocessors. - Alberto Ros 001; Manuel E. Acacio; José M. García 001 (IEEE Trans. Parallel Distributed Syst., 2010)

Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory. - Anurag Negi; Per Stenström; J. Rubén Titos Gil; Manuel E. Acacio; José M. García 001 (PACT, 2011)

Eager Meets Lazy: The Impact of Write-Buffering on Hardware Transactional Memory. - Anurag Negi; J. Rubén Titos Gil; Manuel E. Acacio; José M. García 001; Per Stenström (ICPP, 2011)

ZEBRA: a data-centric, hybrid-policy hardware transactional memory design. - J. Rubén Titos Gil; Anurag Negi; Manuel E. Acacio; José M. García 001; Per Stenström (ICS, 2011)

GLocks: Efficient Support for Highly-Contended Locks in Many-Core CMPs. - José L. Abellán; Juan Fernández 001; Manuel E. Acacio (IPDPS, 2011)

The Impact of Non-coherent Buffers on Lazy Hardware Transactional Memory Systems. - Anurag Negi; J. Rubén Titos Gil; Manuel E. Acacio; José M. García 001; Per Stenström (IPDPS Workshops, 2011)

Design of a collective communication infrastructure for barrier synchronization in cluster-based nanoscale MPSoCs. - José L. Abellán; Juan Fernández Peinador; Manuel E. Acacio; Davide Bertozzi; Daniele Bortolotti; Andrea Marongiu; Luca Benini (DATE, 2012)

Dynamic Last-Level Cache Allocation to Reduce Area and Power Overhead in Directory Coherence Protocols. - Mario Lodde; José Flich; Manuel E. Acacio (Euro-Par, 2012)

π-TM: Pessimistic invalidation for scalable lazy hardware transactional memory. - Anurag Negi; J. Rubén Titos Gil; Manuel E. Acacio; José M. García 001; Per Stenström (HPCA, 2012)

An Experience of Early Initiation to Parallelism in the Computing Engineering Degree at the University of Murcia, Spain. - Manuel E. Acacio; Javier Cuenca 001; Lorenzo Fernández Maimó; Ricardo Fernández-Pascual; Joaquín Cervera; Domingo Giménez; M. Carmen Garrido; Juan A. Sánchez-Laguna; José Guillén; Juan Alejandro Palomino Benito; María-Eugenia Requena (IPDPS Workshops, 2012)

ASCIB: adaptive selection of cache indexing bits for removing conflict misses. - Alberto Ros 001; Polychronis Xekalakis; Marcelo Cintra; Manuel E. Acacio; José M. García 001 (ISLPED, 2012)

Heterogeneous NoC Design for Efficient Broadcast-based Coherence Protocol Support. - Mario Lodde; José Flich; Manuel E. Acacio (NOCS, 2012)

Dynamic Serialization: Improving Energy Consumption in Eager-Eager Hardware Transactional Memory Systems. - Epifanio Gaona-Ramírez; J. Rubén Titos Gil; Manuel E. Acacio; Juan Fernández 001 (PDP, 2012)

Using Heterogeneous Networks to Improve Energy Efficiency in Direct Coherence Protocols for Many-Core CMPs. - Alberto Ros 001; Ricardo Fernández-Pascual; Manuel E. Acacio (SBAC-PAD, 2012)

Hardware transactional memory with software-defined conflicts. - J. Rubén Titos Gil; Manuel E. Acacio; José M. García 001; Tim Harris 001; Adrián Cristal; Osman S. Unsal; Ibrahim Hur; Mateo Valero (ACM Trans. Archit. Code Optim., 2012)

Extending Magny-Cours Cache Coherence. - Alberto Ros 001; Blas Cuesta Saez; Ricardo Fernández-Pascual; María Engracia Gómez; Manuel E. Acacio; Antonio Robles; José M. García 001; José Duato (IEEE Trans. Computers, 2012)

Stencil computations on heterogeneous platforms for the Jacobi method: GPUs versus Cell BE. - José M. Cecilia; José L. Abellán; Juan Fernández 001; Manuel E. Acacio; José M. García 001; Manuel Ujaldon (J. Supercomput., 2012)

Efficient Hardware Barrier Synchronization in Many-Core CMPs. - José L. Abellán; Juan Fernández 001; Manuel E. Acacio (IEEE Trans. Parallel Distributed Syst., 2012)

Deploying Hardware Locks to Improve Performance and Energy Efficiency of Hardware Transactional Memory. - Epifanio Gaona-Ramírez; José L. Abellán; Manuel E. Acacio; Juan Fernández 001 (ARCS, 2013)

Towards Efficient Dynamic LLC Home Bank Mapping with NoC-Level Support. - Mario Lodde; José Flich; Manuel E. Acacio (Euro-Par, 2013)

Efficient Dir0B Cache Coherency for Many-Core CMPs. - José L. Abellán; Alberto Ros 001; Juan Fernández 001; Manuel E. Acacio (ICCS, 2013)

ECONO: Express coherence notifications for efficient cache coherency in many-core CMPs. - José L. Abellán; Alberto Ros 001; Juan Fernández Peinador; Manuel E. Acacio (ICSAMOS, 2013)

On the design of energy-efficient hardware transactional memory systems. - Epifanio Gaona-Ramírez; J. Rubén Titos Gil; Juan Fernández 001; Manuel E. Acacio (Concurr. Comput. Pract. Exp., 2013)

Design of an efficient communication infrastructure for highly contended locks in many-core CMPs. - José L. Abellán; Juan Fernández 001; Manuel E. Acacio (J. Parallel Distributed Comput., 2013)

Efficient Eager Management of Conflicts for Scalable Hardware Transactional Memory. - J. Rubén Titos Gil; Manuel E. Acacio; José M. García 001 (IEEE Trans. Parallel Distributed Syst., 2013)

Eager Beats Lazy: Improving Store Management in Eager Hardware Transactional Memory. - J. Rubén Titos Gil; Anurag Negi; Manuel E. Acacio; José M. García 001; Per Stenström (IEEE Trans. Parallel Distributed Syst., 2013)

Characterization of a List-Based Directory Cache Coherence Protocol for Manycore CMPs. - Ricardo Fernández-Pascual; Alberto Ros 001; Manuel E. Acacio (Euro-Par Workshops (2), 2014)

Selective dynamic serialization for reducing energy consumption in hardware transactional memory systems. - Epifanio Gaona-Ramírez; J. Rubén Titos Gil; Juan Fernández 001; Manuel E. Acacio (J. Supercomput., 2014)

ZEBRA: Data-Centric Contention Management in Hardware Transactional Memory. - J. Rubén Titos Gil; Anurag Negi; Manuel E. Acacio; José M. García 001; Per Stenström (IEEE Trans. Parallel Distributed Syst., 2014)

Early Experiences with Separate Caches for Private and Shared Data. - Juan M. Cebrian; Alberto Ros 001; Ricardo Fernández-Pascual; Manuel E. Acacio (e-Science, 2015)

Adaptive Selection of Cache Indexing Bits for Removing Conflict Misses. - Alberto Ros 001; Polychronis Xekalakis; Marcelo Cintra; Manuel E. Acacio; José M. García 001 (IEEE Trans. Computers, 2015)

Fast and efficient commits for Lazy-Lazy hardware transactional memory. - Epifanio Gaona-Ramírez; José L. Abellán; Manuel E. Acacio (J. Supercomput., 2015)

DASC-DIR: a low-overhead coherence directory for many-core processors. - Alberto Ros 001; Manuel E. Acacio (J. Supercomput., 2015)

Efficient Hardware-Supported Synchronization Mechanisms for Manycores. - José L. Abellán; Juan Fernández 001; Manuel E. Acacio (Handbook on Data Centers, 2015)

Hardware Approaches to Transactional Memory in Chip Multiprocessors. - J. Rubén Titos Gil; Manuel E. Acacio (Handbook on Data Centers, 2015)

Optimization of a Linked Cache Coherence Protocol for Scalable Manycore Coherence. - Ricardo Fernández-Pascual; Alberto Ros 001; Manuel E. Acacio (ARCS, 2016)

Are distributed sharing codes a solution to the scalability problem of coherence directories in manycores? An evaluation study. - Ricardo Fernández-Pascual; Alberto Ros 001; Manuel E. Acacio (J. Supercomput., 2016)

Way-combining directory: an adaptive and scalable low-cost coherence directory. - J. Rubén Titos Gil; Antonio Flores; Ricardo Fernández-Pascual; Alberto Ros 001; Manuel E. Acacio (ICS, 2017)

A dedicated private-shared cache design for scalable multiprocessors. - Juan M. Cebrian; Ricardo Fernández-Pascual; Alexandra Jimborean; Manuel E. Acacio; Alberto Ros 001 (Concurr. Comput. Pract. Exp., 2017)

To be silent or not: on the impact of evictions of clean data in cache-coherent multicores. - Ricardo Fernández-Pascual; Alberto Ros 001; Manuel E. Acacio (J. Supercomput., 2017)

SAWS: Simple and Adaptive Warp Scheduling for Improved Performance in Throughput Processors. - Francisco Muñoz-Martínez; Manuel E. Acacio (PDP, 2018)

Photonic-based express coherence notifications for many-core CMPs. - José L. Abellán; Eduardo Padierna; Alberto Ros 001; Manuel E. Acacio (J. Parallel Distributed Comput., 2018)

On the Parallelization of Stream Compaction on a Low-Cost SDC Cluster. - Gregorio Bernabé; Manuel E. Acacio (Sci. Program., 2018)

Parallel implementations of the 3D fast wavelet transform on a Raspberry Pi 2 cluster. - Gregorio Bernabé; Raúl Hernández; Manuel E. Acacio (J. Supercomput., 2018)

CNN-SIM: A Detailed Arquitectural Simulator of CNN Accelerators. - Francisco Muñoz-Martínez; José L. Abellán; Manuel E. Acacio (Euro-Par Workshops, 2019)

Foreword to the Special Issue on Processors, Interconnects, Storage, and Caches for Exascale Systems. - Manuel E. Acacio; Julio Sahuquillo (Concurr. Comput. Pract. Exp., 2019)

InsideNet: A tool for characterizing convolutional neural networks. - Francisco Muñoz-Martínez; José L. Abellán; Manuel E. Acacio (Future Gener. Comput. Syst., 2019)

Way Combination for an Adaptive and Scalable Coherence Directory. - J. Rubén Titos Gil; Antonio Flores; Ricardo Fernández-Pascual; Alberto Ros 001; Salvador Petit; Julio Sahuquillo; Manuel E. Acacio (IEEE Trans. Parallel Distributed Syst., 2019)

STONNE: A Detailed Architectural Simulator for Flexible Neural Network Accelerators. - Francisco Muñoz-Martínez; José L. Abellán; Manuel E. Acacio; Tushar Krishna (CoRR, 2020)

PfTouch: Concurrent page-fault handling for Intel restricted transactional memory. - J. Rubén Titos Gil; Ricardo Fernández-Pascual; Alberto Ros 001; Manuel E. Acacio (J. Parallel Distributed Comput., 2020)

A Machine Learning Gateway for Scientific Workflow Design. - Brian Broll; Umesh Timalsina; Péter Völgyesi; Tamás Budavári; Ákos Lédeczi; Manuel E. Acacio Sanchez (Sci. Program., 2020)

Ant Colony Optimization-Based Streaming Feature Selection: An Application to the Medical Image Diagnosis. - Labiba Gillani Fahad; Syed Fahad Tahir; Waseem Shahzad; Mehdi Hassan; Hani Alquhayz; Rabia Hassan; Manuel E. Acacio Sanchez (Sci. Program., 2020)

Concurrent Irrevocability in Best-Effort Hardware Transactional Memory. - J. Rubén Titos Gil; Ricardo Fernández-Pascual; Alberto Ros 001; Manuel E. Acacio (IEEE Trans. Parallel Distributed Syst., 2020)

ITSLF: Inter-Thread Store-to-Load Forwardingin Simultaneous Multithreading. - Josué Feliu; Alberto Ros 001; Manuel E. Acacio; Stefanos Kaxiras (MICRO, 2021)

A novel network fabric for efficient spatio-temporal reduction in flexible DNN accelerators. - Francisco Muñoz-Martínez; José L. Abellán; Manuel E. Acacio; Tushar Krishna (NOCS, 2021)

STONNE: Enabling Cycle-Level Microarchitectural Simulation for DNN Inference Accelerators. - Francisco Muñoz-Martínez; José L. Abellán; Manuel E. Acacio; Tushar Krishna (IEEE Comput. Archit. Lett., 2021)

A Taxonomy for Classification and Comparison of Dataflows for GNN Accelerators. - Raveesh Garg; Eric Qin 001; Francisco Muñoz-Martínez; Robert Guirado; Akshay Jain 001; Sergi Abadal; José L. Abellán; Manuel E. Acacio; Eduard Alarcón; Sivasankaran Rajamanickam; Tushar Krishna (CoRR, 2021)

Understanding the Design-Space of Sparse/Dense Multiphase GNN dataflows on Spatial Accelerators. - Raveesh Garg; Eric Qin 001; Francisco Muñoz-Martínez; Robert Guirado; Akshay Jain 001; Sergi Abadal; José L. Abellán; Manuel E. Acacio; Eduard Alarcón; Sivasankaran Rajamanickam; Tushar Krishna (IPDPS, 2022)

Analysis of the Interactions Between ILP and TLP With Hardware Transactional Memory. - Víctor Nicolás-Conesa; J. Rubén Titos Gil; Ricardo Fernández-Pascual; Alberto Ros 001; Manuel E. Acacio (PDP, 2022)

Analysing software prefetching opportunities in hardware transactional memory. - Marina Shimchenko; J. Rubén Titos Gil; Ricardo Fernández-Pascual; Manuel E. Acacio; Stefanos Kaxiras; Alberto Ros 001; Alexandra Jimborean (J. Supercomput., 2022)

DeTraS: Delaying Stores for Friendly-Fire Mitigation in Hardware Transactional Memory. - J. Rubén Titos Gil; Ricardo Fernández-Pascual; Alberto Ros 001; Manuel E. Acacio (IEEE Trans. Parallel Distributed Syst., 2022)

CELLO: Compiler-Assisted Efficient Load-Load Ordering in Data-Race-Free Regions. - Sawan Singh; Josué Feliu; Manuel E. Acacio; Alexandra Jimborean; Alberto Ros 001 (PACT, 2023)

Flexagon: A Multi-dataflow Sparse-Sparse Matrix Multiplication Accelerator for Efficient DNN Processing. - Francisco Muñoz-Martínez; Raveesh Garg; Michael Pellauer; José L. Abellán; Manuel E. Acacio; Tushar Krishna (ASPLOS (3), 2023)

Speculative inter-thread store-to-load forwarding in SMT architectures. - Josué Feliu; Alberto Ros 001; Manuel E. Acacio; Stefanos Kaxiras (J. Parallel Distributed Comput., 2023)

STIFT: A Spatio-Temporal Integrated Folding Tree for Efficient Reductions in Flexible DNN Accelerators. - Francisco Muñoz-Martínez; José L. Abellán; Manuel E. Acacio; Tushar Krishna (ACM J. Emerg. Technol. Comput. Syst., 2023)

Chaining Transactions for Effective Concurrency Management in Hardware Transactional Memory. - Víctor Nicolás-Conesa; J. Rubén Titos Gil; Ricardo Fernández-Pascual; Manuel E. Acacio; Alberto Ros 001 (MICRO, 2024)

On the interactions between ILP and TLP with hardware transactional memory. - Víctor Nicolás-Conesa; J. Rubén Titos Gil; Ricardo Fernández-Pascual; Alberto Ros 001; Manuel E. Acacio (Microprocess. Microsystems, 2024)

ACTA: Automatic Configuration of the Tensor Memory Accelerator for High-End GPUs. - Nicolás Meseguer; Yifan Sun 002; Michael Pellauer; José L. Abellán; Manuel E. Acacio (GPGPU@PPoPP, 2025)

No Rush in Executing Atomic Instructions. - Ashkan Asgharzadeh; Josué Feliu; Manuel E. Acacio; Stefanos Kaxiras; Alberto Ros 001 (HPCA, 2025)

WoperTM: Got Nacks? Use Them! - Víctor Nicolás-Conesa; J. Rubén Titos Gil; Ricardo Fernández-Pascual; Manuel E. Acacio; Alberto Ros 001 (IEEE Comput. Archit. Lett., 2025)

Precise characterization of coherence activity in multicores using gem5. - Joaquín Ferrer; Juan M. Cebrian; Ricardo Fernández-Pascual; Manuel E. Acacio (J. Supercomput., 2025)