Hydra: An Accelerator for Real-Time Edge-Aware Permeability Filtering in 65nm CMOS. - Manuel Eggimann; Christelle Gloor; Florian Scheidegger; Lukas Cavigelli; Michael Schaffner; Aljosa Smolic; Luca Benini (ISCAS, 2018)

Low Power Embedded Gesture Recognition Using Novel Short-Range Radar Sensors. - Manuel Eggimann; Jonas Erb; Philipp Mayer; Michele Magno; Luca Benini (IEEE SENSORS, 2019)

An Energy Efficient System for Touch Modality Classification in Electronic Skin Applications. - Mario Osta; Ali Ibrahim; Michele Magno; Manuel Eggimann; Antonio Pullini; Paolo Gastaldo; Maurizio Valle (ISCAS, 2019)

A RISC-V Based Open Hardware Platform for Always-On Wearable Smart Sensing. - Manuel Eggimann; Stefan Mach; Michele Magno; Luca Benini (IWASI, 2019)

HR-SAR-Net: A Deep Neural Network for Urban Scene Segmentation from High-Resolution SAR Data. - Xiaying Wang; Lukas Cavigelli; Manuel Eggimann; Michele Magno; Luca Benini (CoRR, 2019)

InfiniWolf: Energy Efficient Smart Bracelet for Edge Computing with Dual Source Energy Harvesting. - Michele Magno; Xiaying Wang; Manuel Eggimann; Lukas Cavigelli; Luca Benini (DATE, 2020)

4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. - Davide Rossi; Francesco Conti 001; Manuel Eggimann; Stefan Mach; Alfio Di Mauro; Marco Guermandi; Giuseppe Tagliavini; Antonio Pullini; Igor Loi; Jie Chen 042; Eric Flamand; Luca Benini (ISSCC, 2021)

Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. - Davide Rossi; Francesco Conti 001; Manuel Eggimann; Alfio Di Mauro; Giuseppe Tagliavini; Stefan Mach; Marco Guermandi; Antonio Pullini; Igor Loi; Jie Chen 042; Eric Flamand; Luca Benini (CoRR, 2021)

TinyRadarNN: Combining Spatial and Temporal Convolutional Neural Networks for Embedded Gesture Recognition With Short Range Radars. - Moritz Scherer 001; Michele Magno; Jonas Erb; Philipp Mayer; Manuel Eggimann; Luca Benini (IEEE Internet Things J., 2021)

ImpediSense: A long lasting wireless wearable bio-impedance sensor node. - Kanika S. Dheman; Philipp Mayer; Manuel Eggimann; Simone Schuerle; Michele Magno (Sustain. Comput. Informatics Syst., 2021)

A 5 μW Standard Cell Memory-Based Configurable Hyperdimensional Computing Accelerator for Always-on Smart Sensing. - Manuel Eggimann; Abbas Rahimi; Luca Benini (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode. - Davide Rossi; Francesco Conti 001; Manuel Eggimann; Alfio Di Mauro; Giuseppe Tagliavini; Stefan Mach; Marco Guermandi; Antonio Pullini; Igor Loi; Jie Chen 042; Eric Flamand; Luca Benini (IEEE J. Solid State Circuits, 2022)

Siracusa: A Low-Power On-Sensor RISC-V SoC for Extended Reality Visual Processing in 16nm CMOS. - Moritz Scherer 001; Manuel Eggimann; Alfio Di Mauro; Arpan Suravi Prasad; Francesco Conti 001; Davide Rossi; Jorge Tomás Gómez; Ziyun Li; Syed Shakib Sarwar; Zhao Wang; Barbara De Salvo; Luca Benini (ESSCIRC, 2023)

A 12.4TOPS/W @ 136GOPS AI-IoT System-on-Chip with 16 RISC-V, 2-to-8b Precision-Scalable DNN Acceleration and 30%-Boost Adaptive Body Biasing. - Francesco Conti 001; Davide Rossi; Gianna Paulin; Angelo Garofalo; Alfio Di Mauro; Georg Rutishauser; Gianmarco Ottavi; Manuel Eggimann; Hayate Okuhara; Vincent Huard; Olivier Montfort; Lionel Jure; et al. (ISSCC, 2023)

Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC with 2-to-8b DNN Acceleration and 30%-Boost Adaptive Body Biasing. - Francesco Conti 001; Gianna Paulin; Davide Rossi; Alfio Di Mauro; Georg Rutishauser; Gianmarco Ottavi; Manuel Eggimann; Hayate Okuhara; Luca Benini (CoRR, 2023)

Near-Memory Computing Architectures and Circuits for Ultra-Low Power Near-Sensor Processors. - Manuel Eggimann (2023)

PELS: A Lightweight and Flexible Peripheral Event Linking System for Ultra-Low Power IoT Processors. - Alessandro Ottaviano; Robert Balas; Philippe Sauter; Manuel Eggimann; Luca Benini (DATE, 2024)

Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET. - Gianna Paulin; Paul Scheffler; Thomas Benz; Matheus A. Cavalcante; Tim Fischer 001; Manuel Eggimann; Yichao Zhang 003; Nils Wistoff; Luca Bertaccini; Luca Colagrande; Gianmarco Ottavi; Frank K. Gürkaynak; et al. (VLSI Technology and Circuits, 2024)

Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2-8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing. - Francesco Conti 001; Gianna Paulin; Angelo Garofalo; Davide Rossi; Alfio Di Mauro; Georg Rutishauser; Gianmarco Ottavi; Manuel Eggimann; Hayate Okuhara; Luca Benini (IEEE J. Solid State Circuits, 2024)

Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality With At-MRAM Neural Engine. - Arpan Suravi Prasad; Moritz Scherer 001; Francesco Conti 001; Davide Rossi; Alfio Di Mauro; Manuel Eggimann; Jorge Tomás Gómez; Ziyun Li; Syed Shakib Sarwar; Zhao Wang; Barbara De Salvo; Luca Benini (IEEE J. Solid State Circuits, 2024)

Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12nm FinFET. - Paul Scheffler; Thomas Benz; Viviane Potocnik; Tim Fischer 001; Luca Colagrande; Nils Wistoff; Yichao Zhang 003; Luca Bertaccini; Gianmarco Ottavi; Manuel Eggimann; Matheus A. Cavalcante; Gianna Paulin; et al. (CoRR, 2025)

A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications. - Angelo Garofalo; Alessandro Ottaviano; Matteo Perotti; Thomas Benz; Yvan Tortorella; Robert Balas; Michael Rogenmoser; Chi Zhang; Luca Bertaccini; Nils Wistoff; Maicol Ciani; Cyril Koenig; et al. (CoRR, 2025)

Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12-nm FinFET. - Paul Scheffler; Thomas Benz; Viviane Potocnik; Tim Fischer 001; Luca Colagrande; Nils Wistoff; Yichao Zhang 003; Luca Bertaccini; Gianmarco Ottavi; Manuel Eggimann; Matheus A. Cavalcante; Gianna Paulin; et al. (IEEE J. Solid State Circuits, 2025)