Sine-Wave Signal Characterization Using Square-Wave and SigmaDelta-Modulation: Application to Mixed-Signal BIST. - Diego Vázquez; Gloria Huertas; África Luque; Manuel J. Barragan Asian; Gildas Léger; Adoración Rueda; José Luis Huertas (J. Electron. Test., 2005)

A Sinewave Analyzer for Mixed-Signal BIST Applications in a 0.35µm Technology. - Manuel J. Barragan Asian; Diego Vázquez; Adoración Rueda (DDECS, 2006)

Interactive presentation: BIST method for die-level process parameter variation monitoring in analog/mixed-signal integrated circuits. - Amir Zjajo; Manuel J. Barragan Asian; José Pineda de Gyvez (DATE, 2007)

Practical Implementation of a Network Analyzer for Analog BIST Applications. - Manuel J. Barragan Asian; Diego Vázquez; Adoración Rueda (DATE, 2008)

A BIST Solution for the Functional Characterization of RF Systems Based on Envelope Response Analysis. - Manuel J. Barragan Asian; Rafaella Fiorelli; Diego Vázquez; Adoración Rueda; José Luis Huertas (Asian Test Symposium, 2009)

(Some) Open Problems to Incorporate BIST in Complex Heterogeneous Integrated Systems. - Manuel J. Barragan Asian; Gloria Huertas; Adoración Rueda; José Luis Huertas (DELTA, 2010)

Low-cost signature test of RF blocks based on envelope response analysis. - Manuel J. Barragan Asian; Rafaella Fiorelli; Diego Vázquez; Adoración Rueda; José Luis Huertas (ETS, 2010)

On-chip biased voltage-controlled oscillator with temperature compensation of the oscillation amplitude for robust I/Q generation. - Antonio J. Ginés; Ricardo Doldán; Manuel J. Barragan Asian; Adoración Rueda; Eduardo J. Peralías (ISCAS, 2010)

A BIST Solution for Frequency Domain Characterization of Analog Circuits. - Manuel J. Barragan Asian; Diego Vázquez; Adoración Rueda (J. Electron. Test., 2010)

Improving the Accuracy of RF Alternate Test Using Multi-VDD Conditions: Application to Envelope-Based Test of LNAs. - Manuel J. Barragan Asian; Rafaella Fiorelli; Gildas Léger; Adoración Rueda; José L. Huertas (Asian Test Symposium, 2011)

Alternate Test of LNAs Through Ensemble Learning of On-Chip Digital Envelope Signatures. - Manuel J. Barragan Asian; Rafaella Fiorelli; Gildas Léger; Adoración Rueda; José L. Huertas (J. Electron. Test., 2011)

Analog Sinewave Signal Generators for Mixed-Signal Built-in Test Applications. - Manuel J. Barragan Asian; Diego Vázquez; Adoración Rueda (J. Electron. Test., 2011)

OBT for settling error test of sampled-data systems using signal-dependent clocking. - Manuel J. Barragan Asian; Gildas Léger; José L. Huertas (ETS, 2012)

Multi-condition alternate test of analog, mixed-signal, and RF systems. - Manuel J. Barragan Asian; Gildas Léger; José Luis Huertas (LATW, 2012)

Digital Adaptive Calibration of Multi-Step Analog to Digital Converters. - Amir Zjajo; Manuel J. Barragan Asian; José Pineda de Gyvez (J. Low Power Electron., 2012)

Low-Power Die-Level Process Variation and Temperature Monitors for Yield Analysis and Optimization in Deep-Submicron CMOS. - Amir Zjajo; Manuel J. Barragan Asian; José Pineda de Gyvez (IEEE Trans. Instrum. Meas., 2012)

Efficient selection of signatures for analog/RF alternate test. - Manuel J. Barragan Asian; Gildas Léger (ETS, 2013)

Sinusoidal signal generation for mixed-signal BIST using a harmonic-cancellation technique. - Manuel J. Barragán; Gildas Léger; Diego Vázquez; Adoración Rueda (LASCAS, 2013)

On-Chip Implementation of an Integrator-Based Servo-Loop for ADC Static Linearity Test. - Guillaume Renaud; Manuel J. Barragán; Salvador Mir; Marc Sabut (ATS, 2014)

Evaluation of digital ternary stimuli for dynamic test of ΣΔ ADCs. - Matthieu Dubois; Haralampos-G. D. Stratigopoulos; Salvador Mir; Manuel J. Barragán (VLSI-SoC, 2014)

Statistical Evaluation of Digital Techniques for $ sum varDelta$ ADC BIST. - Matthieu Dubois; Haralampos-G. D. Stratigopoulos; Salvador Mir; Manuel J. Barragán (VLSI-SoC (Selected Papers), 2014)

Feature selection for alternate test using wrappers: application to an RF LNA case study. - Manuel J. Barragán; Gildas Léger (DATE, 2015)

Evaluation of low-cost mixed-signal test techniques for circuits with long simulation times. - Haralampos-G. D. Stratigopoulos; Manuel J. Barragán; Salvador Mir; Hervé Le Gall; Neha Bhargava; Ankur Bal (ITC, 2015)

Special session: Hot topics: Statistical test methods. - Manuel J. Barragán; Gildas Léger; Florence Azaïs; Ronald D. Blanton; Adit D. Singh; Stephen Sunter (VTS, 2015)

A Procedure for Alternate Test Feature Design and Selection. - Manuel J. Barragan Asian; Gildas Léger (IEEE Des. Test, 2015)

Linearity test of high-speed high-performance ADCs using a self-testable on-chip generator. - Antonio J. Ginés; Eduardo J. Peralías; Gildas Léger; Adoración Rueda; Guillaume Renaud; Manuel J. Barragán; Salvador Mir (ETS, 2016)

Questioning the reliability of Monte Carlo simulation for machine learning test validation. - Gildas Léger; Manuel J. Barragán (ETS, 2016)

Practical Simulation Flow for Evaluating Analog/Mixed-Signal Test Techniques. - Manuel J. Barragán; Haralampos-G. D. Stratigopoulos; Salvador Mir; Hervé Le Gall; Neha Bhargava; Ankur Bal (IEEE Des. Test, 2016)

A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs. - Guillaume Renaud; Manuel J. Barragán; Asma Laraba; Haralampos-G. D. Stratigopoulos; Salvador Mir; Hervé Le Gall; Hervé Naudet (J. Electron. Test., 2016)

Brownian distance correlation-directed search: A fast feature selection technique for alternate test. - Gildas Léger; Manuel J. Barragán (Integr., 2016)

A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio ΣΔ ADC. - Manuel J. Barragán; Rshdee Alhakim; Haralampos-G. D. Stratigopoulos; Matthieu Dubois; Salvador Mir; Hervé Le Gall; Neha Bhargava; Ankur Bal (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

On the limits of machine learning-based test: A calibrated mixed-signal system case study. - Manuel J. Barragán; Gildas Léger; Antonio J. Ginés; Eduardo J. Peralías; Adoración Rueda (DATE, 2017)

Design of a sinusoidal signal generator with calibrated harmonic cancellation for mixed-signal BIST in a 28 nm FDSOI technology. - Hani Malloug; Manuel J. Barragan Asian; Salvador Mir; Laurent Basteres; Hervé Le Gall (ETS, 2017)

Mixed-signal BIST computation offloading using IEEE 1687. - Michele Portolan; Manuel J. Barragán; Rshdee Alhakim; Salvador Mir (ETS, 2017)

Analysis of an efficient on-chip servo-loop technique for reduced-code static linearity test of pipeline ADCs. - Guillaume Renaud; Marc Margalef-Rovira; Manuel J. Barragán; Salvador Mir (VTS, 2017)

Guest Editorial: Analog, Mixed-Signal and RF Testing. - Manuel J. Barragán; William R. Eisenstadt (J. Electron. Test., 2017)

Assisted test design for non-intrusive machine learning indirect test of millimeter-wave circuits. - Florent Cilici; Manuel J. Barragán; Salvador Mir; Estelle Lauga-Larroze; Sylvain Bourdel (ETS, 2018)

Reduced-code static linearity test of SAR ADCs using a built-in incremental ∑Δ converter. - Renato S. Feitoza; Manuel J. Barragán; Salvador Mir; Daniel Dzahini (IOLTS, 2018)

Mixed-signal test automation: Are we there yet? - Gildas Léger; Manuel J. Barragán (ISCAS, 2018)

An oscillation-based test technique for on-chip testing of mm-wave phase shifters. - Marc Margalef-Rovira; Manuel J. Barragán; Ekta Sharma; Philippe Ferrari; Emmanuel Pistono; Sylvain Bourdel (VTS, 2018)

Guest Editorial: Special Issue on Analog, Mixed-Signal, and RF Testing. - Ke Huang 001; Manuel J. Barragán (J. Electron. Test., 2018)

Practical Harmonic Cancellation Techniques for the On-Chip Implementation of Sinusoidal Signal Generators for Mixed-Signal BIST Applications. - Hani Malloug; Manuel J. Barragán; Salvador Mir (J. Electron. Test., 2018)

On the use of causal feature selection in the context of machine-learning indirect test. - Manuel J. Barragán; Gildas Léger; Florent Cilici; Estelle Lauga-Larroze; Sylvain Bourdel; Salvador Mir (DATE, 2019)

A 52 dB-SFDR 166 MHz sinusoidal signal generator for mixed-signal BIST applications in 28 nm FDSOI technology. - Hani Malloug; Manuel J. Barragán; Salvador Mir (ETS, 2019)

Yield Recovery of mm-Wave Power Amplifiers using Variable Decoupling Cells and One-Shot Statistical Calibration. - Florent Cilici; Manuel J. Barragán; Salvador Mir; Estelle Lauga-Larroze; Sylvain Bourdel; Gildas Léger (ISCAS, 2019)

Feature selection and feature design for machine learning indirect test: a tutorial review. - Manuel J. Barragán; Gildas Léger (SMACD, 2019)

Efficient generation of data sets for one-shot statistical calibration of RF/mm-wave circuits. - Florent Cilici; Gildas Léger; Manuel J. Barragán; Salvador Mir; Estelle Lauga-Larroze; Sylvain Bourdel (SMACD, 2019)

Reduced-Code Techniques for On-Chip Static Linearity Test of SAR ADCs. - Renato S. Feitoza; Manuel J. Barragán; Salvador Mir (VLSI-SoC, 2019)

Fully Differential 4-V Output Range 14.5-ENOB Stepwise Ramp Stimulus Generator for On-Chip Static Linearity Test of ADCs. - Guillaume Renaud; Mamadou Diallo; Manuel J. Barragán; Salvador Mir (IEEE Trans. Very Large Scale Integr. Syst., 2019)

On-chip reduced-code static linearity test of Vcm-based switching SAR ADCs using an incremental analog-to-digital converter. - Renato S. Feitoza; Manuel J. Barragán; Antonio J. Ginés; Salvador Mir (ETS, 2020)

A Comprehensive End-to-end Solution for a Secure and Dynamic Mixed-signal 1687 System. - Michele Portolan; R. Silveira Feitoza; Ghislain Takam Tchendjou; Vincent Reynaud; Kalpana Senthamarai Kannan; Manuel J. Barragán; Emmanuel Simeu; Paolo Maistri; Lorena Anghel; Régis Leveugle; Salvador Mir (IOLTS, 2020)

Static linearity BIST for Vcm-based switching SAR ADCs using a reduced-code measurement technique. - Renato S. Feitoza; Manuel J. Barragán; Antonio J. Ginés; Salvador Mir (NEWCAS, 2020)

mm-Wave Through-Load Switch for in-situ Vector Network Analyzer on a 55-nm BiCMOS Technology. - Marc Margalef-Rovira; Abdelhalim A. Saadi; Sylvain Bourdel; Manuel J. Barragán; Emmanuel Pistono; Christophe Gaquière; Philippe Ferrari (NEWCAS, 2020)

Design of a 77-GHz LC-VCO With a Slow-Wave Coplanar Stripline-Based Inductor. - Ekta Sharma; Abdelhalim A. Saadi; Marc Margalef-Rovira; Emmanuel Pistono; Manuel J. Barragán; Antonio Augusto Lisboa de Souza; Philippe Ferrari; Sylvain Bourdel (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

Analysis and mitigation of timing inaccuracies in high-frequency on-chip sinusoidal signal generators based on harmonic cancellation. - Ankush Mamgain; Manuel J. Barragán; Salvador Mir (ETS, 2021)

A gm/ID Design Methodology for 28 nm FD-SOI CMOS Resistive Feedback LNAs. - Sylvain Bourdel; Serge Subias; Mohamed Khalil Bouchoucha; Manuel J. Barragán; Andreia Cathelin; Carlos Galup-Montoro (ICECS, 2021)

Integrated Wideband Millimeter-Wave Bias-Tee - Application to Distributed Amplifier Biasing. - Mohamad El-Chaar; Antonio Augusto Lisboa de Souza; Manuel J. Barragán; Florence Podevin; Sylvain Bourdel; Jean-Daniel Arnould (NEWCAS, 2021)

mm-Wave Single-Pole Double-Throw switches: HBT- vs MOSFET-based designs. - Marc Margalef-Rovira; Christophe Gaquière; Antonio Augusto Lisboa de Souza; Loic Vincent; Manuel J. Barragán; Emmanuel Pistono; Florence Podevin; Philippe Ferrari (NEWCAS, 2021)

Guest Editorial Special Issue on the IEEE International NEWCAS Conference 2020. - Jean-Pierre David; Manuel J. Barragán (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

mm-Wave Through-Load Element for On-Wafer Measurement Applications. - Marc Margalef-Rovira; Olivier Occello; Abdelhalim A. Saadi; Vanessa Avramovic; Sylvie Lépilliet; Loic Vincent; Manuel J. Barragán; Emmanuel Pistono; Sylvain Bourdel; Christophe Gaquière; Philippe Ferrari (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

On-chip calibration for high-speed harmonic cancellation-based sinusoidal signal generators. - Ankush Mamgain; Salvador Mir; Jai Narayan Tripathi; Manuel J. Barragán (ATS, 2022)

Special Session on RF/5G Test. - William R. Eisenstadt; Mark Roos; Devin Morris; José Luis González-Jiménez; Christopery Mounet; Manuel J. Barragán; Gildas Léger; Florent Cilici; Estelle Lauga-Larroze; Salvador Mir; Sylvain Bourdel; Marc Margalef-Rovira; et al. (ETS, 2022)

A methodology for defect detection in analog circuits based on causal feature selection. - Gildas Léger; Antonio J. Ginés; Valentin Gutierrez; Manuel J. Barragán (ICECS 2022, 2022)

N-Path Mixer with Wide Rejection Including the 7th Harmonic for Low Power Multi-standard Receivers. - Ali Al Shakoush; Sana Ibrahim; Serge Subias; Florence Podevin; Manuel J. Barragán; Dayana A. Pino-Monroy; Imadeddine Bendjeddou; Estelle Lauga-Larroze; Laurent Fesquet; Thierry Taris; Sylvain Bourdel (NEWCAS, 2022)

A self-referenced on-chip jitter BIST with sub-picosecond resolution in 28 nm FD-SOI technology. - Manasa Madhvaraj; Salvador Mir; Manuel J. Barragán (VLSI-SoC, 2022)

Innovative Practices Track: Innovative Analog Circuit Testing Technologies. - Chris Mangelsdorf; Manasa Madhvaraj; Salvador Mir; Manuel J. Barragán; Daisuke Iimori; Takayuki Nakatani; Shogo Katayama; Gaku Ogihara; Yujie Zhao; Jianglin Wei; Anna Kuwana; Kentaroh Katoh; et al. (VTS, 2022)

Design-Oriented All-Regime All-Region 7-Parameter Short-Channel MOSFET Model Based on Inversion Charge. - Dayana A. Pino-Monroy; Patrick Scheer; Mohamed Khalil Bouchoucha; Carlos Galup-Montoro; Manuel J. Barragán; Philippe Cathelin; Jean-Michel Fournier; Andreia Cathelin; Sylvain Bourdel (IEEE Access, 2022)

A Survey on Sub-6 GHz Wideband LNAs for Ultra- Low-Power IoT applications. - Mohamed Khalil Bouchoucha; Mathieu Coustans; Manuel J. Barragán; Andreia Cathelin; Sylvain Bourdel (IEEE DataPort, 2022)

A wideband sub-6GHz continuously tunable gm-boosted CG Low Noise Amplifier in 28 nm FD-SOI CMOS technology. - Mohamed Khalil Bouchoucha; Manuel J. Barragán; Andreia Cathelin; Sylvain Bourdel (ESSCIRC, 2023)

Performance benchmark of State-of-the-art Sub-6-GHz wideband LNAs Based on an Extensive Survey. - Mohamed Khalil Bouchoucha; Mathieu Coustans; Manuel J. Barragán; Andreia Cathelin; Sylvain Bourdel (ISCAS, 2023)

Resistive Feedback LNA design using a 7-parameter design-oriented model for advanced technologies. - Mohamed Khalil Bouchoucha; Dayana A. Pino-Monroy; Patrick Scheer; Philippe Cathelin; Jean-Michel Fournier; Manuel J. Barragán; Andreia Cathelin; Sylvain Bourdel (ISCAS, 2023)

A harmonic cancellation-based high-frequency on-chip sinusoidal signal generator with calibration using a coarse-fine delay cell. - Ankush Mamgain; Salvador Mir; Jai Narayan Tripathi; Manuel J. Barragán (ISCAS, 2023)

Design-oriented model for short-channel MOS transistors based on inversion charge. - Dayana A. Pino-Monroy; Patrick Scheer; Mohamed Khalil Bouchoucha; Carlos Galup-Montoro; Manuel J. Barragán; Jean-Michel Fournier; Andreia Cathelin; Sylvain Bourdel (LASCAS, 2023)

Special Session: On-chip jitter BIST with sub-picosecond resolution at GHz frequencies. - Manasa Madhvaraj; Salvador Mir; Manuel J. Barragán (LATS, 2023)

Special Session: A high-frequency sinusoidal signal generation using harmonic cancellation. - Ankush Mamgain; Salvador Mir; Jai Narayan Tripathi; Manuel J. Barragán (LATS, 2023)

A sub-picosecond resolution jitter instrument for GHz frequencies based on a sub-sampling TDA. - Ankush Mamgain; Manasa Madhvaraj; Salvador Mir; Manuel J. Barragán; Jai Narayan Tripathi (NEWCAS, 2023)

A 5-DC-parameter MOSFET model for circuit simulation in QucsStudio and SPECTRE. - Deni Germano Alves Neto; Cristina Missel Adotnes; Gabriel Maranhão; Mohamed Khalil Bouchoucha; Manuel J. Barragán; Andreia Cathelin; Márcio Cherem Schneider; Sylvain Bourdel; Carlos Galup-Montoro (NEWCAS, 2023)

Corrections to "Design-Oriented All-Regime All-Region 7-Parameter Short-Channel MOSFET Model Based on Inversion Charge". - Dayana A. Pino-Monroy; Patrick Scheer; Mohamed Khalil Bouchoucha; Carlos Galup-Montoro; Manuel J. Barragán; Philippe Cathelin; Jean-Michel Fournier; Andreia Cathelin; Sylvain Bourdel (IEEE Access, 2023)

Dynamic Analysis of RF CMOS Inverter-Based Ring Oscillators using an All-Region MOSFET Charge-Based Model in 28nm FD-SOI CMOS. - Julien Poupon; Manuel J. Barragán; Andreia Cathelin; Sylvain Bourdel (ISCAS, 2024)

An Integrated Miniaturized VNA for On-Chip PA Mismatch Measurement. - Oumayma Belkhadra; Gilles Montoriol; Emmanuel Pistone; Hugo Vallee; Florent Cilici; Manuel J. Barragán; Salvador Mir; Sylvain Bourdel (NewCAS, 2024)

Zero-Overhead Nonintrusive Test of mmW Integrated Circuits Based on Wafer-Level Parametric Tests. - Olivier Occello; Marc Margalef-Rovira; Manuel J. Barragan Asian; C. Durand; A. Rhellab; Loic Vincent; Jordan Corsi; Sylvie Lépilliet; G. Ducournau; P. Ferrari (NewCAS, 2024)

Design and Evaluation of a 10 GHz LNA with Balun and Diodes for HBM and CDM ESD Protection in 28 nm CMOS FD-SOI. - Thalis Da C. Guedes; Johan Bourgeat; Manuel J. Barragán; Jean-Marc Duchamp; Philippe Ferrari (SBCCI, 2024)

Design-Oriented Single-Piece 5-DC-Parameter MOSFET Model. - Deni Germano Alves Neto; Mohamed Khalil Bouchoucha; Gabriel Maranhão; Manuel J. Barragán; Márcio Cherem Schneider; Andreia Cathelin; Sylvain Bourdel; Carlos Galup-Montoro (IEEE Access, 2024)

Design-Oriented Single-Piece Explicit I-V DC Charge-Based Model for MOS Transistors in Nanometric Technologies. - Julien Poupon; Manuel J. Barragan Asian; Andreia Cathelin; Sylvain Bourdel (IEEE Access, 2024)

Wideband Tunable N-Path Mixer With Calibrated Harmonic Rejection Including the 7th LO Harmonic. - Sana Ibrahim; Ali Al Shakoush; Serge Subias; Loic Vincent; Manuel J. Barragan Asian; Laurent Fesquet; Florence Podevin; Sylvain Bourdel (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

N-Path Filtering and Mixing Analysis - A General Approach Based on Fourier Transform. - Florence Podevin; Imadeddine Bendjeddou; Fadel Mohsen; Catalin Andrei Dobrin; Sana Ibrahim; Ali Al Shakoush; Mamadou Diallo; Jordan Corsi; Loic Vincent; Manuel J. Barragan Asian; Sylvain Bourdel (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)