Asynchronous Modular Arbiter. - J. Calvo; José I. Acha; Manuel Valencia-Barrero (IEEE Trans. Computers, 1986)

Modeling of real bistables in VHDL. - Antonio J. Acosta 001; Angel Barriga; Manuel Valencia-Barrero; Manuel J. Bellido; José L. Huertas (EURO-DAC, 1993)

A New Faster Method for Calculating the Resolution Coefficient of CMOS Latches: Design of an Optimum Latch. - Manuel J. Bellido; Manuel Valencia-Barrero; Antonio J. Acosta 001; Angel Barriga; José Luis Huertas; Rafael Domínguez-Castro (ISCAS, 1993)

New CMOS VLSI linear self-timed architectures. - Antonio J. Acosta 001; Manuel J. Bellido; Manuel Valencia-Barrero; Angel Barriga; Raúl Jiménez; José L. Huertas (ASYNC, 1995)

Modular Asynchronous Arbiter Insensitive to Metastability. - Manuel Valencia-Barrero; Manuel J. Bellido; José L. Huertas; Antonio J. Acosta 001; Santiago Sánchez-Solano (IEEE Trans. Computers, 1995)

SODS: a new CMOS differential-type structure. - Antonio J. Acosta 001; Manuel Valencia 001; Angel Barriga; Manuel J. Bellido; José L. Huertas (IEEE J. Solid State Circuits, 1995)

Efficient self-timed circuits based on weak NMOS-trees. - Raúl Jiménez; Antonio J. Acosta 001; Angel Barriga; Manuel J. Bellido; Manuel Valencia 001 (ICECS, 1998)

Inertial and degradation delay model for CMOS logic gates. - Jorge Juan-Chico; Paulino Ruiz-de-Clavijo; Manuel J. Bellido; Antonio J. Acosta 001; Manuel Valencia 001 (ISCAS, 2000)

Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits. - Antonio J. Acosta 001; Raúl Jiménez; Jorge Juan-Chico; Manuel J. Bellido; Manuel Valencia-Barrero (PATMOS, 2000)

Degradation Delay Model Extension to CMOS Gates. - Jorge Juan-Chico; Manuel J. Bellido; Paulino Ruiz-de-Clavijo; Antonio J. Acosta 001; Manuel Valencia-Barrero (PATMOS, 2000)

HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model. - Paulino Ruiz-de-Clavijo; Jorge Juan-Chico; Manuel J. Bellido; Antonio J. Acosta 001; Manuel Valencia-Barrero (DATE, 2001)

AUTODDM: automatic characterization tool for the delay degradation model. - Jorge Juan-Chico; Manuel J. Bellido; Paulino Ruiz-de-Clavijo; Carmen Baena Oliva; Manuel Valencia 001 (ICECS, 2001)

Gate-level simulation of CMOS circuits using the IDDM model. - Manuel J. Bellido; Jorge Juan-Chico; Paulino Ruiz-de-Clavijo; Antonio J. Acosta 001; Manuel Valencia-Barrero (ISCAS (5), 2001)

Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level. - Carmen Baena Oliva; Jorge Juan-Chico; Manuel J. Bellido; Paulino Ruiz-de-Clavijo; Carlos Jesús Jiménez-Fernández; Manuel Valencia 001 (PATMOS, 2002)

Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1. - Pilar Parra Fernández; Antonio J. Acosta 001; Manuel Valencia-Barrero (PATMOS, 2002)

Selective Clock-Gating for Low-Power Synchronous Counters. - Pilar Parra Fernández; Antonio J. Acosta 001; Raúl Jiménez; Manuel Valencia-Barrero (J. Low Power Electron., 2005)

A switching noise vision of the optimization techniques for low-power synthesis. - Javier Castro-Ramirez; Pilar Parra Fernández; Manuel Valencia-Barrero; Antonio J. Acosta 001 (ECCTD, 2007)

Asymmetric clock driver for improved power and noise performances. - Javier Castro-Ramirez; Pilar Parra Fernández; Manuel Valencia-Barrero; Antonio J. Acosta 001 (ISCAS, 2007)

Logic Synthesis. - Angel Barriga; Carlos Jesús Jiménez-Fernández; Manuel Valencia-Barrero (Wiley Encyclopedia of Computer Science and Engineering, 2008)

Low Power Implementation of Trivium Stream Cipher. - José Miguel Mora-Gutierrez; Carlos Jesús Jiménez-Fernández; Manuel Valencia-Barrero (PATMOS, 2012)

Fault attack on FPGA implementations of Trivium stream cipher. - Francisco Eugenio Potestad-Ordóñez; Carlos Jesús Jiménez-Fernández; Manuel Valencia-Barrero (ISCAS, 2016)

Trivium hardware implementations for power reduction. - José Miguel Mora-Gutierrez; Carlos Jesús Jiménez-Fernández; Manuel Valencia-Barrero (Int. J. Circuit Theory Appl., 2017)

Multiradix Trivium Implementations for Low-Power IoT Hardware. - José Miguel Mora-Gutierrez; Carlos Jesús Jiménez-Fernández; Manuel Valencia-Barrero (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Vulnerability Analysis of Trivium FPGA Implementations. - Francisco Eugenio Potestad-Ordóñez; Carlos Jesús Jiménez-Fernández; Manuel Valencia-Barrero (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Floorplanning as a practical countermeasure against clock fault attack in Trivium stream cipher. - Francisco Eugenio Potestad-Ordóñez; Carlos Jesús Jiménez-Fernández; Carmen Baena Oliva; Pilar Parra Fernández; Manuel Valencia-Barrero (DCIS, 2018)

Hamming-Code Based Fault Detection Design Methodology for Block Ciphers. - Francisco Eugenio Potestad-Ordóñez; Erica Tena-Sánchez; Ricardo Chaves; Manuel Valencia-Barrero; Antonio Acosta-Jiménez; Carlos Jesús Jiménez-Fernández (ISCAS, 2020)

An Academic Approach to FPGA Design Based on a Distance Meter Circuit. - Carlos Jesús Jiménez-Fernández; Carmen Baena Oliva; Pilar Parra Fernández; Francisco Eugenio Potestad-Ordóñez; Manuel Valencia-Barrero (Rev. Iberoam. de Tecnol. del Aprendiz., 2020)

Breaking Trivium Stream Cipher Implemented in ASIC Using Experimental Attacks and DFA. - Francisco Eugenio Potestad-Ordóñez; Manuel Valencia-Barrero; Carmen Baena Oliva; Pilar Parra Fernández; Carlos Jesús Jiménez-Fernández (Sensors, 2020)

ASIC Design and Power Characterization of Standard and Low Power Multi-Radix Trivium. - José Miguel Mora-Gutierrez; Carlos Jesús Jiménez-Fernández; Manuel Valencia-Barrero (IEEE Trans. Circuits Syst., 2020)

Trivium Stream Cipher Countermeasures Against Fault Injection Attacks and DFA. - Francisco Eugenio Potestad-Ordóñez; Erica Tena-Sánchez; José Miguel Mora-Gutierrez; Manuel Valencia-Barrero; Carlos Jesús Jiménez-Fernández (IEEE Access, 2021)

Experimental FIA Methodology Using Clock and Control Signal Modifications under Power Supply and Temperature Variations. - Francisco Eugenio Potestad-Ordóñez; Erica Tena-Sánchez; José Miguel Mora-Gutierrez; Manuel Valencia-Barrero; Carlos Jesús Jiménez-Fernández (Sensors, 2021)