A 0.1-3GHz cell-based fractional-N all digital phase-locked loop using ΔΣ noise-shaped phase detector. - Yao-Chia Liu; Wei-Zen Chen; Mao-Hsuan Chou; Tsung-Hsien Tsai; Yen-Wei Lee; Min-Shueh Yuan (CICC, 2013)

A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application. - Mu-Shan Lin; Chien-Chun Tsai; Chih-Hsien Chang; Wen-Hung Huang; Ying-Yu Hsu; Shu-Chun Yang; Chin-Ming Fu; Mao-Hsuan Chou; Tien-Chien Huang; Ching-Fang Chen; Tze-Chiang Huang; Saman Adham; et al. (IEEE J. Solid State Circuits, 2014)

Embedded PLL Phase Noise Measurement Based on a PFD/CP MASH 1-1-1 ΔΣ Time-to-Digital Converter in 7nm CMOS. - Mao-Hsuan Chou; Ya-Tin Chang; Tsung-Hsien Tsai; Tsung-Che Lu; Chia-Chun Liao; Hung-Yi Kuo; Ruey-Bin Sheen; Chih-Hsien Chang; Kenny C.-H. Hsieh; Alvin Leng Sun Loke; Mark Chen 001 (VLSI Circuits, 2020)