A low-complexity LDPC decoder for NAND flash applications. - Mao-Ruei Li; Hsueh-Chih Chou; Yeong-Luh Ueng; Yun Chen 001 (ISCAS, 2014)

A 5.4 µW Soft-Decision BCH Decoder for Wireless Body Area Networks. - Chia-Hsiang Yang; Ting-Ying Huang; Mao-Ruei Li; Yeong-Luh Ueng (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

An IDD receiver of LDPC coded modulation scheme for flash memory applications. - Mao-Ruei Li; Ting-Yu Kuan; Huang-Chang Lee; Yeong-Luh Ueng (APCCAS, 2016)

A modified gradient descent bit flipping decoding scheme for LDPC codes. - Mao-Ruei Li; Li-Min Jhuang; Yeong-Luh Ueng (SiPS, 2017)

A 5.28-Gb/s LDPC Decoder With Time-Domain Signal Processing for IEEE 802.15.3c Applications. - Mao-Ruei Li; Chia-Hsiang Yang; Yeong-Luh Ueng (IEEE J. Solid State Circuits, 2017)

Optimization Techniques for the Efficient Implementation of High-Rate Layered QC-LDPC Decoders. - Huang-Chang Lee; Mao-Ruei Li; Jyun-Kai Hu; Po-Chiao Chou; Yeong-Luh Ueng (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

An Efficient Combined Bit-Flipping and Stochastic LDPC Decoder Using Improved Probability Tracers. - Yeong-Luh Ueng; Chun-Yi Wang; Mao-Ruei Li (IEEE Trans. Signal Process., 2017)

A Shuffled-Based Iterative Demodulation and Decoding Scheme for Ldpc Coded Flash Memory. - Li-Chung Lee; Wei-Min Lai; Mao-Ruei Li; Yeong-Luh Ueng (ICASSP, 2018)

Hardware-friendly LDPC Decoding Scheduling for 5G HARQ Applications. - Cing-Yi Liang; Mao-Ruei Li; Huang-Chang Lee; Hsin-Yu Lee; Yeong-Luh Ueng (ICASSP, 2019)

An Efficient High-Rate Non-Binary LDPC Decoder Architecture With Early Termination. - Mao-Ruei Li; Wei-Xiang Chu; Huang-Chang Lee; Yeong-Luh Ueng (IEEE Access, 2019)

An Efficient Short High-Order Non-Binary LDPC Decoder Architecture Using a Message-Adaptation EMS Algorithm. - Wei-Xiang Chu; Ting-An Hu; Huang-Chang Lee; Mao-Ruei Li; Yeong-Luh Ueng (IEEE Access, 2021)