An HMAC processor with integrated SHA-1 and MD5 algorithms. - Mao-Yin Wang; Chih-Pin Su; Chih-Tsun Huang; Cheng-Wen Wu (ASP-DAC, 2004)

Area and Test Cost Reduction for On-Chip Wireless Test Channels with System-Level Design Techniques. - Chun-Kai Hsu; Li-Ming Denq; Mao-Yin Wang; Jing-Jia Liou; Chih-Tsun Huang; Cheng-Wen Wu (ATS, 2008)

Single- and Multi-core Configurable AES Architectures for Flexible Security. - Mao-Yin Wang; Chih-Pin Su; Chia-Lung Horng; Cheng-Wen Wu; Chih-Tsun Huang (IEEE Trans. Very Large Scale Integr. Syst., 2010)

A Mesh-Structured Scalable IPsec Processor. - Mao-Yin Wang; Cheng-Wen Wu (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Monitoring and timing prediction in early analyzing and checking performance of interconnection networks at ESL. - Mao-Yin Wang; Jen-Chieh Yeh (ISQED, 2012)

A Smart Saddle for the Status Monitoring of Guide Dogs. - Mao-Yin Wang; Tung-Jing Fang; Lih-Jen Kau; Wen-Dih Yeh; Jwo-Shiun Sun (ICCE-Taiwan, 2024)

An Obstacles Closest Path Planning Algorithm for Automatic Local Routing of Vehicles. - Mao-Yin Wang; Sun-Yen Tan; Yu-Ting Tu; Lih-Jen Kau (ICCE-Taiwan, 2024)