Load scheduling: Reducing pressure on distributed register files for free. - Mei Wen; Nan Wu 003; Maolin Guan; Chunyuan Zhang (ASP-DAC, 2008)

On-Chip Memory System Optimization Design for the FT64 Scientific Stream Accelerator. - Mei Wen; Nan Wu 003; Chunyuan Zhang; Qianming Yang; Ju Ren 002; Yi He 008; Wei Wu; Jun Chai; Maolin Guan; Changqing Xun (IEEE Micro, 2008)

Tiled Multi-Core Stream Architecture. - Nan Wu 003; Qianming Yang; Mei Wen; Yi He 008; Ju Ren 002; Maolin Guan; Chunyuan Zhang (Trans. High Perform. Embed. Archit. Compil., 2011)

Fully Distributed On-chip Instruction Memory Design for Stream Architecture Based on Field-Divided VLIW Compression. - Yi He 008; Maolin Guan; Chunyuan Zhang; Tian Tian; Qianming Yang (HPCC-ICESS, 2012)

Pre-Migration of Vehicle to Network Services Based on Priority in Mobile Edge Computing. - Xiang Yu; Maolin Guan; Mingxia Liao; Xia Fan (IEEE Access, 2019)