Application Specific Instruction set processor specialized for block motion estimation. - Marc-André Daigneault; J. M. Pierre Langlois; Jean-Pierre David (ICCD, 2008)

Towards 5ps resolution TDC on a dynamically reconfigurable FPGA (abstract only). - Marc-André Daigneault; Jean-Pierre David (FPGA, 2010)

A High-Resolution Time-to-Digital Converter on FPGA Using Dynamic Reconfiguration. - Marc-André Daigneault; Jean-Pierre David (IEEE Trans. Instrum. Meas., 2011)

Raising the abstraction level of HDL for control-dominant applications. - Marc-André Daigneault; Jean-Pierre David (FPL, 2012)

Synchronized-transfer-level design methodology applied to hardware matrix multiplication. - Marc-André Daigneault; Jean-Pierre David (ReConFig, 2012)

High-Level Description and Synthesis of Floating-Point Accumulators on FPGA. - Marc-André Daigneault; Jean-Pierre David (FCCM, 2013)

Hardware description and synthesis of control-intensive reconfigurable dataflow architectures (abstract only). - Marc-André Daigneault; Jean-Pierre David (FPGA, 2013)

Fast description and synthesis of control-dominant circuits. - Marc-André Daigneault; Jean-Pierre David (Comput. Electr. Eng., 2014)

Intermediate-Level Synthesis of a Gauss-Jordan Elimination Linear Solver. - Marc-André Daigneault; Jean-Pierre David (IPDPS Workshops, 2015)

Automated Synthesis of Streaming Transfer Level Hardware Designs. - Marc-André Daigneault; Jean-Pierre David (ACM Trans. Reconfigurable Technol. Syst., 2018)