Sub-1V, Robust and Compact 6T SRAM cell in Double Gate MOS technology. - Olivier Thomas; Marina Reyboz; Marc Belleville (ISCAS, 2007)

Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier. - Bettina Rebaud; Marc Belleville; Christian Bernard; Zeqin Wu; Michel Robert; Philippe Maurine; Nadine Azémard (ISVLSI, 2008)

On-chip data compression for I.R. image sensors. - Tristan Thabuis; Patrick Villard; Marc Belleville; Gilles Sicard; Frederic Pistone; Patrick Maillart; Gilbert Decaens (ICECS, 2009)

Digital Timing Slack Monitors and Their Specific Insertion Flow for Adaptive Compensation of Variabilities. - Bettina Rebaud; Marc Belleville; Edith Beigné; Christian Bernard; Michel Robert; Philippe Maurine; Nadine Azémard (PATMOS, 2009)

3D Integration for Digital and Imagers Circuits: Opportunities and Challenges. - Marc Belleville (PATMOS, 2010)

An On-Chip Multi-Mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-Power Domain SoC Using a 65-nm Standard CMOS Logic Process. - Motoi Ichihashi; Hélène Lhermet; Edith Beigné; Frédéric Rothan; Marc Belleville; Amara Amara (J. Low Power Electron., 2010)

Energy autonomous sensor systems: Towards a ubiquitous sensor technology. - Marc Belleville; Hervé Fanet; Paolo Fiorini; Pierre Nicole; Marcel J. M. Pelgrom; Christian Piguet; Robert Hahn; Chris Van Hoof; Ruud J. M. Vullers; Marco Tartagni; Eugenio Cantatore (Microelectron. J., 2010)

Comparison of 65nm LP bulk and LP PD-SOI with adaptive power gate body bias for an LDPC codec. - Julien Le Coz; Philippe Flatresse; Sylvain Engels; Alexandre Valentian; Marc Belleville; Christine Raynaud; Damien Croain; Pascal Urard (ISSCC, 2011)

Timing slack monitoring under process and environmental variations: Application to a DSP performance optimization. - Bettina Rebaud; Marc Belleville; Edith Beigné; Christian Bernard; Michel Robert; Philippe Maurine; Nadine Azémard (Microelectron. J., 2011)

Design challenges for nano-scale devices. - Marc Belleville; Olivier Thomas; Alexandre Valentian; Fabien Clermidy (ESSDERC, 2012)

Multi-application electrical stimulator architecture dedicated to waveform control by electrode-tissue impedance spectra monitoring. - Florent Dupont; Cyril Condemine; Jean-François Beche; Marc Belleville (ICECS, 2012)

A mixed LPDDR2 impedance calibration technique exploiting 28nm Fully-Depleted SOI Back-Biasing. - Dimitri Soussan; Alexandre Valentian; Sylvain Majcherczak; Marc Belleville (ICICDT, 2012)

Selected Articles from the VARI 2011 Workshop. - Nadine Azémard; Marc Belleville (J. Low Power Electron., 2012)

Ultra-Thin Body and Buried Oxide (UTBB) FDSOI Technology with Low Variability and Power Management Capability for 22 nm Node and Below. - J. Mazurier; Olivier Weber; François Andrieu; Alain Toffoli; Olivier Thomas; Fabienne Allain; Jean-Philippe Noel; Marc Belleville; Olivier Faynot; T. Poiroux (J. Low Power Electron., 2012)

A gate level methodology for efficient statistical leakage estimation in complex 32nm circuits. - Smriti Joshi; Anne Lombardot; Marc Belleville; Edith Beigné; Stéphane Girard (DATE, 2013)

Computing detection probability of delay defects in signal line tsvs. - Carolina Metzler; Aida Todri-Sanial; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Arnaud Virazel; Pascal Vivet; Marc Belleville (ETS, 2013)

An efficient metric of setup time for pulsed flip-flops based on output transition time. - Sebastien Bernard; Alexandre Valentian; Marc Belleville; David Bol; Jean-Didier Legat (ICICDT, 2013)

A CBRAM-based compact interconnect switch for non-volatile reconfigurable logic circuits. - Santhosh Onkaraiah; Marc Belleville; Marina Reyboz; Fabien Clermidy; Elisa Vianello; Jean-Michel Portal; Christophe Muller (ICICDT, 2013)

A novel method to mitigate TSV electromigration for 3D ICs. - Yuanqing Cheng; Aida Todri-Sanial; Alberto Bosio; Luigi Dillio; Patrick Girard 001; Arnaud Virazel; Pascal Vivet; Marc Belleville (ISVLSI, 2013)

Experimental analysis of flip-flops minimum operating voltage in 28nm FDSOI and the impact of back bias and temperature. - Sebastien Bernard; Marc Belleville; Alexandre Valentian; Jean-Didier Legat; David Bol (PATMOS, 2014)

A Robust and Energy Efficient Pulse-Triggered Flip-Flop Design for Ultra Low Voltage Operations. - Sebastien Bernard; Alexandre Valentian; David Bol; Jean-Didier Legat; Marc Belleville (J. Low Power Electron., 2014)

Dedicated network for distributed configuration in a mixed-signal Wireless Sensor Node circuit. - Soundous Chairat; Edith Beigné; Marc Belleville (PATMOS, 2015)

Power-Clock Generator Impact on the Performance of NEM-Based Quasi-Adiabatic Logic Circuits. - Samer Houri; Gérard Billiot; Marc Belleville; Alexandre Valentian; Hervé Fanet (RC, 2015)

Limits of CMOS Technology and Interest of NEMS Relays for Adiabatic Logic Applications. - Samer Houri; Gérard Billiot; Marc Belleville; Alexandre Valentian; Hervé Fanet (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Guest Editorial Special Issue on Nanoelectronic Circuit and System Design Methods for the Mobile Computing Era. - Aida Todri-Sanial; Saraju P. Mohanty; Mariane Comte; Marc Belleville (ACM J. Emerg. Technol. Comput. Syst., 2016)

Ultra-wide voltage range pulse-triggered flip-flops and register file with tunable energy-delay target in 28 nm UTBB-FDSOI. - Sebastien Bernard; Marc Belleville; Jean-Didier Legat; Alexandre Valentian; David Bol (Microelectron. J., 2016)

Adaptive Architectures, Circuits and Technology Solutions for Future IoT Systems. - Marc Belleville; Anca Molnos; Gilles Sicard; Jean-Frédéric Christmann; Dominique Morche; Duy-Hieu Bui; Diego Puschini; Suzanne Lesecq; Edith Beigné (J. Low Power Electron., 2017)