A hierarchic task-based programming model for distributed heterogeneous computing. - Jorge Ejarque; Marc Domínguez; Rosa M. Badia (Int. J. High Perform. Comput. Appl., 2019)

DVINO: A RISC-V Vector Processor Implemented in 65nm Technology. - Guillem Cabo; Gerard Candón; Xavier Carril; Max Doblas; Marc Domínguez; Alberto González 004; César Hernández; Víctor Jiménez; Vatistas Kostalampros; Rubén Langarita; Neiel Leyva; Guillem López-Paradís; et al. (DCIS, 2022)

Sargantana: An Academic SoC RISC-V Processor in 22nm FDSOI Technology. - Max Doblas; Gerard Candón; Xavier Carril; Marc Domínguez; Enric Erra; Alberto González 004; César Hernández; Víctor Jiménez; Vatistas Kostalampros; Rubén Langarita; Neiel Leyva; Guillem López-Paradís; et al. (DCIS, 2023)

Functional Verification of a RISC-V Vector Accelerator. - Víctor Jiménez; Mario Rodríguez; Marc Domínguez; Josep Sans; Ivan Diaz; Luca Valente; Vito Luca Guglielmi; Josue V. Quiroga; R. Ignacio Genovese; Nehir Sönmez; Oscar Palomar; Miquel Moretó (IEEE Des. Test, 2023)