High-level synthesis scheduling and allocation using genetic algorithms. - Marc J. M. Heijligers; L. J. M. Cluitmans; Jochen A. G. Jess (ASP-DAC, 1995)

A Constructive Method for Exploiting Code Motion. - Luiz C. V. dos Santos; Marc J. M. Heijligers; C. A. J. van Eijk; Jos T. J. van Eijndhoven; Jochen A. G. Jess (ISSS, 1996)

A code-motion pruning technique for global scheduling. - Luiz C. V. dos Santos; Marc J. M. Heijligers; C. A. J. van Eijk; J. Van Eijnhoven; Jochen A. G. Jess (ACM Trans. Design Autom. Electr. Syst., 2000)

Statistical Power Estimation of Behavioral Descriptions. - B. Arts; N. van der Eng; Marc J. M. Heijligers; H. Munk; Frans Theeuwen; Luca Benini; Enrico Macii; A. Milia; Roberto Maro; A. Bellu (PATMOS, 2003)

A Scalable Architecture for LDPC Decodin. - Mauro Cocco; John Dielissen; Marc J. M. Heijligers; Andries Hekstra; Jos Huisken (DATE, 2004)

Compositional Memory Systems for Data Intensive Applications. - Anca Mariana Molnos; Marc J. M. Heijligers; Sorin Cotofana; Jos T. J. van Eijndhoven (DATE, 2004)

Compositional Memory Systems for Multimedia Communicating Tasks. - Anca Mariana Molnos; Marc J. M. Heijligers; Sorin Dan Cotofana; Jos T. J. van Eijndhoven (DATE, 2005)

Compositional, efficient caches for a chip multi-processor. - Anca Mariana Molnos; Marc J. M. Heijligers; Sorin Dan Cotofana; Jos T. J. van Eijndhoven (DATE, 2006)

Throughput optimization via cache partitioning for embedded multiprocessors. - Anca Mariana Molnos; Sorin Dan Cotofana; Marc J. M. Heijligers; Jos T. J. van Eijndhoven (ICSAMOS, 2006)

An Embedded Low Power High Efficient Object Tracker for Surveillance Systems. - Isael Diaz; Marc J. M. Heijligers; Richard P. Kleihorst; Alexander Danilin (ICDSC, 2007)

XETAL-II: A 107 GOPS, 600mW Massively-Parallel Processor for Video Scene Analysis. - Anteneh A. Abbo; Richard P. Kleihorst; Vishal Choudhary; Leo Sevat; Paul Wielage; Sebastien Mouy; Marc J. M. Heijligers (ISSCC, 2007)

Static Cache Partitioning Robustness Analysis for Embedded On-Chip Multi-processors. - Anca Mariana Molnos; Sorin Dan Cotofana; Marc J. M. Heijligers; Jos T. J. van Eijndhoven (Trans. High Perform. Embed. Archit. Compil., 2007)

Compositional, dynamic cache management for embedded chip multiprocessors. - Anca Mariana Molnos; Marc J. M. Heijligers; Sorin Dan Cotofana (DATE, 2008)

Xetal-II: A 107 GOPS, 600 mW Massively Parallel Processor for Video Scene Analysis. - Anteneh A. Abbo; Richard P. Kleihorst; Vishal Choudhary; Leo Sevat; Paul Wielage; Sebastien Mouy; Bart Vermeulen; Marc J. M. Heijligers (IEEE J. Solid State Circuits, 2008)

Compositional, Dynamic Cache Management for Embedded Chip Multiprocessors. - Anca Mariana Molnos; Sorin Cotofana; Marc J. M. Heijligers; Jos T. J. van Eijndhoven (J. Signal Process. Syst., 2009)