Increasing Design Productivity through Core Reuse, Meta-data Encapsulation, and Synthesis. - Adam Arnesen; Kevin Ellsworth; Derrick Gibelyou; Travis Haroldsen; Jared Havican; Marc Padilla; Brent E. Nelson; Michael Rice; Michael J. Wirthlin (FPL, 2010)

Using Hard Macros to Reduce FPGA Compilation Time. - Christopher Lavin; Marc Padilla; Subhrashankha Ghosh; Brent E. Nelson; Brad L. Hutchings; Michael J. Wirthlin (FPL, 2010)

Rapid prototyping tools for FPGA designs: RapidSmith. - Christopher Lavin; Marc Padilla; Philip Lundrigan; Brent E. Nelson; Brad L. Hutchings (FPT, 2010)

HMFlow: Accelerating FPGA Compilation with Hard Macros for Rapid Prototyping. - Christopher Lavin; Marc Padilla; Jaren Lamprecht; Philip Lundrigan; Brent E. Nelson; Brad L. Hutchings (FCCM, 2011)

RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs. - Christopher Lavin; Marc Padilla; Jaren Lamprecht; Philip Lundrigan; Brent E. Nelson; Brad L. Hutchings (FPL, 2011)

Assessing the Temporal Stability of the Accuracy of a Time Series of Burned Area Products. - Marc Padilla; Stephen V. Stehman; Javier Litago; Emilio Chuvieco (Remote. Sens., 2014)