Power supply noise and logic error probability. - Dennis Andrade; Ferran Martorell; Marc Pons 001; Francesc Moll; Antonio Rubio 001 (ECCTD, 2007)

VCTA: A Via-Configurable Transistor Array regular fabric. - Marc Pons 001; Francesc Moll; Antonio Rubio 001; Jaume Abella 001; Xavier Vera; Antonio González 001 (VLSI-SoC, 2010)

Design of complex circuits using the Via-Configurable transistor array regular layout fabric. - Marc Pons 001; Francesc Moll; Antonio Rubio 001; Jaume Abella 001; Xavier Vera; Antonio González 001 (SoCC, 2011)

Fixed origin corner square inspection layout regularity metric. - Marc Pons 001; Marc-Nicolas Morgan; Christian Piguet (DATE, 2012)

Maximum delay variation temperature-aware standard cell design. - Marc Pons 001; Jean-Luc Nagel; Christian Piguet (ICECS, 2012)

Ultra low-power standard cell design using planar bulk CMOS in subthreshold operation. - Marc Pons 001; Jean-Luc Nagel; Daniel Séverac; Marc-Nicolas Morgan; Daniel Sigg; Pierre-François Rüedi; Christian Piguet (PATMOS, 2013)

Sub-Threshold Design and Architectural Choices. - Christian Piguet; Marc Pons 001; Daniel Séverac (ISVLSI, 2015)

Sub-threshold latch-based icyflex2 32-bit processor with wide supply range operation. - Marc Pons 001; Thanh-Chau Le; Claude Arm; Daniel Séverac; Jean-Luc Nagel; Marc-Nicolas Morgan; Stéphane Emery (ESSCIRC, 2016)

Ultra low power microelectronics for wearable and medical devices. - Pierre-François Rüedi; A. Bishof; Marcin K. Augustyniak; Pascal Persechini; Jean-Luc Nagel; Marc Pons 001; Stéphane Emery; Olivier Chételat (DATE, 2017)

A 0.5 V 2.5 μW/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13nW/kB SRAM Retention in 55nm Deeply-Depleted Channel CMOS. - Marc Pons 001; Christoph Thomas Müller; David Ruffieux; Jean-Luc Nagel; Stéphane Emery; Andreas Burg 001; Shuuji Tanahashi; Yoshitaka Tanaka; Atsushi Takeuchi (CICC, 2019)

A 20 Channel EMG SoC with an Integrated 32b RISC Core for Real-Time Wireless Prosthetic Control. - Marc Pons Solé; Andre Bischof; Lorenzo Bergamini; Philippe Dallemagne; Stéphane Emery; Komail M. H. Badami; Jiang Deng; Themistoklis Mavrogordatos; Erfan Azarkhish; Loïc Zahnd; Costantino Cosentino; Marcin K. Augustyniak; et al. (ESSCIRC, 2019)

WiseTOP: a quality of service-aware low power acquisition and wireless communication platform for prosthesis control. - Lorenzo Bergamini; Marc Pons Solé; Jean-Dominique Decotignie; Philippe Dallemagne (ICECS, 2019)

Energy-Autonomous MCU Operating in sub-VT Regime with Tightly-Integrated Energy-Harvester : A SoC for IoT smart nodes containing a MCU with minimum-energy point of 2.9pJ/cycle and a harvester with output power range from sub-µW to 4.32mW. - Jian Deng; Jean-Luc Nagel; Loïc Zahnd; Marc Pons 001; David Ruffieux; Claude Arm; Pascal Persechini; Stéphane Emery (ISLPED, 2019)

Minimum Energy Point in Constant Frequency Designs under Adaptive Supply Voltage and Body Bias Adjustment in 55 nm DDC. - Christoph Thomas Müller; Marc Pons 001; David Ruffieux; Jean-Luc Nagel; Stéphane Emery; Andreas Burg 001; Shuuji Tanahashi; Yoshitaka Tanaka; Atsushi Takeuchi (PRIME, 2019)

Single-Battery Cooperative Sensors For Multi-Lead Long Term Ambulatory ECG Measurement. - Komail M. H. Badami; Marc Pons Solé; Erfan Azarkhish; André Fivaz; Michaël Rapin; Olivier Chételat; Stéphane Emery (BioCAS, 2021)

Ultra-low-power Physical Activity Classifier for Wearables: From Generic MCUs to ASICs. - Enric M. Calvo; Philippe Renevey; Mathieu Lemay; Andrea Bonetti; Marc Pons Solé; Régis Cattenoz; Stéphane Emery; Ricard Delgado-Gonzalo (EMBC, 2021)

A Construction Kit for Efficient Low Power Neural Network Accelerator Designs. - Petar Jokic; Erfan Azarkhish; Andrea Bonetti; Marc Pons 001; Stéphane Emery; Luca Benini (ACM Trans. Embed. Comput. Syst., 2022)