Motion estimation VLSI architecture for image coding. - Gilles Privat; Marc Renaudin (ICCD, 1989)

Asynchronous relaxation of locally-coupled automata networks, with application to parallel VLSI implementation of iterative image processing algorithms. - Patricia Planet; Gilles Privat; Marc Renaudin (ASAP, 1993)

A general time domain approach for the design of perfect reconstruction modulated filter banks. - Michel Poize; Marc Renaudin; Patrick Venier (ICASSP (3), 1993)

SMILE: A scalable microcontroller library element. - A. K. Betts; Ivo Bolsens; Etienne Sicard; Marc Renaudin; Adrian Johnstone (Microprocess. Microprogramming, 1993)

The Design of Fast Asynchronous Adder Structures and their Implementation Using D.C.V.S. Logic. - Marc Renaudin; Bachar El-Hassan (ISCAS, 1994)

A Fine-Grain Asynchronous VLSI Cellular Array Processor Architecture. - Gilles Privat; Frédéric Robin; Marc Renaudin; Bachar El-Hassan (ISCAS, 1995)

Asynchronous SRT Dividers: The Real Cost. - Hicham Boutamine; Alain Guyot; Bachar El-Hassan; Marc Renaudin (ED&TC, 1996)

Self timed division and square-root extraction. - Alain Guyot; Marc Renaudin; Bachar El-Hassan; Volker Levering (VLSI Design, 1996)

A new asynchronous pipeline scheme: application to the design of a self-timed ring divider. - Marc Renaudin; Bachar El-Hassan; Alain Guyot (IEEE J. Solid State Circuits, 1996)

Asynchronous Relaxation of Morphological Operators: A Joint Algorithm-Architecture Perspective. - Frédéric Robin; Gilles Privat; Marc Renaudin (Int. J. Pattern Recognit. Artif. Intell., 1997)

ASPRO-216: A Standard-Cell Q.D.I. 16-Bit RISC Asynchronous Microprocessor. - Marc Renaudin; Pascal Vivet; Frédéric Robin (ASYNC, 1998)

A Design Framework for Asynchronous/Synchronous Circuits Based on CHP to VHDL Translation. - Marc Renaudin; Pascal Vivet; Frédéric Robin (ASYNC, 1999)

Low-power systems on chips (SOCs). - Christian Piguet; Marc Renaudin; Thierry J.-F. Omnés (DATE, 2001)

Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems. - Jean-Baptiste Rigaud; Jerome Quartana; Laurent Fesquet; Marc Renaudin (VLSI-SOC, 2001)

A new contactless smart card IC using an on-chip antenna and an asynchronous microcontroller. - André Abrial; Jacky Bouvier; Marc Renaudin; Patrice Senn; Pascal Vivet (IEEE J. Solid State Circuits, 2001)

High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems. - Jean-Baptiste Rigaud; Laurent Fesquet; Marc Renaudin; Jerome Quartana (DATE, 2002)

Implementing Asynchronous Circuits on LUT Based FPGAs. - Quoc Thai Ho; Jean-Baptiste Rigaud; Laurent Fesquet; Marc Renaudin; Robin Rolland (FPL, 2002)

Watershed parallel algorithm for asynchronous processors array. - Bruno Galilée; Franck Mamalet; Marc Renaudin; Pierre-Yves Coulon (ICME (1), 2002)

Synthesis of QDI Asynchronous Circuits from DTL-Style Petri-Net. - Anh Vu Dihn Duc; Laurent Fesquet; Marc Renaudin (IWLS, 2002)

Low-Power Asynchronous A/D Conversion. - Emmanuel Allier; Laurent Fesquet; Marc Renaudin; Gilles Sicard (PATMOS, 2002)

Dynamic Voltage Scheduling for Real Time Asynchronous Systems. - Mohammed Es Salhiene; Laurent Fesquet; Marc Renaudin (PATMOS, 2002)

A New Class of Asynchronous A/D Converters Based on Time Quantization. - Emmanuel Allier; Gilles Sicard; Laurent Fesquet; Marc Renaudin (ASYNC, 2003)

An Approach to the Introduction of Formal Validation in an Asynchronous Circuit Design Flow. - Dominique Borrione; Menouer Boubekeur; Emil Dumitrescu; Marc Renaudin; Jean-Baptiste Rigaud; Antoine Siriani (HICSS, 2003)

Power/Area Tradeoffs in 1-of-M Parallel-Prefix Asynchronous Adders. - João Leonardo Fragoso; Gilles Sicard; Marc Renaudin (PATMOS, 2003)

Statistic Implementation of QDI Asynchronous Primitives. - Philippe Maurine; Jean-Baptiste Rigaud; G. Fraidy Bouesse; Gilles Sicard; Marc Renaudin (PATMOS, 2003)

Automatic Generation of 1-of-M QDI Asynchronous Adders. - João Leonardo Fragoso; Gilles Sicard; Marc Renaudin (SBCCI, 2003)

Validation of asynchronous circuit specifications using IF/CADP. - Dominique Borrione; Menouer Boubekeur; Laurent Mounier; Marc Renaudin; Antoine Siriani (VLSI-SOC, 2003)

Asynchronous FIR Filters: Towards a New Digital Processing Chain. - F. Aeschlimann; Emmanuel Allier; Laurent Fesquet; Marc Renaudin (ASYNC, 2004)

High Security Smartcards. - Marc Renaudin; G. Fraidy Bouesse; Ph. Proust; J. P. Tual; Laurent Sourgen; Fabien Germain (DATE, 2004)

Asynchronous Circuits Sensitivity to Fault Injection. - Yannick Monnet; Marc Renaudin; Régis Leveugle (IOLTS, 2004)

TAST Profiler and Low Energy Asynchronous Design Methodology. - Kamel Slimani; Yann Rémond; Gilles Sicard; Marc Renaudin (PATMOS, 2004)

La technologie asynchrone au service de la réduction d'énergie dans les systèmes embarqués. - Laurent Fesquet; Mohammed Es Salhiene; Marc Renaudin (Ann. des Télécommunications, 2004)

A current shaping methodology for lowering em disturbances in asynchronous circuits. - Dhanistha Panyasak; Gilles Sicard; Marc Renaudin (Microelectron. J., 2004)

An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework. - Edith Beigné; Fabien Clermidy; Pascal Vivet; Alain Clouard; Marc Renaudin (ASYNC, 2005)

Asynchronous circuits transient faults sensitivity evaluation. - Yannick Monnet; Marc Renaudin; Régis Leveugle (DAC, 2005)

DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement. - G. Fraidy Bouesse; Marc Renaudin; Sophie Dumont; Fabien Germain (DATE, 2005)

FPGA Architecture for Multi-Style Asynchronous Logic. - N. Huot; H. Dubreuil; Laurent Fesquet; Marc Renaudin (DATE, 2005)

A clock-less low-voltage AES crypto-processor. - G. Fraidy Bouesse; Marc Renaudin; Adrien Witon; Fabien Germain (ESSCIRC, 2005)

Wireless sensor network node with asynchronous architecture and vibration harvesting micro power generator. - Yasser Ammar; Aurélien Buhrig; Marcin Marzencki; Benoît Charlot; Skandar Basrour; Karine Matou; Marc Renaudin (sOc-EUSAI, 2005)

A Programmable Logic Architecture for Prototyping Clockless Circuits. - Laurent Fesquet; Marc Renaudin (FPL, 2005)

GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips. - Jerome Quartana; Salim Renane; Arnaud Baixas; Laurent Fesquet; Marc Renaudin (FPL, 2005)

Hardening Techniques against Transient Faults for Asynchronous Circuits. - Yannick Monnet; Marc Renaudin; Régis Leveugle (IOLTS, 2005)

A 120nm low power asynchronous ADC. - Emmanuel Allier; Julien Goulier; Gilles Sicard; Alessandro Dezzani; Eric André; Marc Renaudin (ISLPED, 2005)

Asynchrnous Architecture for Sensor Network Nodes. - Aurélien Buhrig; Marc Renaudin; Dominique Barthel (Med-Hoc-Net, 2005)

A Method to Design Compact Dual-rail Asynchronous Primitives. - Alin Razafindraibe; Michel Robert; Marc Renaudin; Philippe Maurine (PATMOS, 2005)

Power Consumption Reduction Using Dynamic Control of Micro Processor Performance. - David Rios-Arambula; Aurélien Buhrig; Marc Renaudin (PATMOS, 2005)

Asynchronous Systems on Programmable Logic. - Laurent Fesquet; Jerome Quartana; Marc Renaudin (ReCoSoC, 2005)

Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals. - G. Fraidy Bouesse; Marc Renaudin; Gilles Sicard (VLSI-SoC, 2005)

Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits. - Bertrand Folco; Vivian Brégier; Laurent Fesquet; Marc Renaudin (VLSI-SoC, 2005)

Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping. - Jerome Quartana; Laurent Fesquet; Marc Renaudin (VLSI-SoC, 2005)

AsyncRFID: Fully Asynchronous Contactless Systems, Providing High Data Rates, Low Power and Dynamic Adaptation. - D. Caucheteux; Edith Beigné; Elisabeth Crochon; Marc Renaudin (ASYNC, 2006)

Path Swapping Method to Improve DPA Resistance of Quasi Delay Insensitive Asynchronous Circuits. - G. Fraidy Bouesse; Gilles Sicard; Marc Renaudin (CHES, 2006)

Spectral analysis of a signal driven sampling scheme. - Saeed Mian Qaisar; Laurent Fesquet; Marc Renaudin (EUSIPCO, 2006)

Case Study of a Fault Attack on Asynchronous DES Crypto-Processors. - Yannick Monnet; Marc Renaudin; Régis Leveugle; Christophe Clavier; Pascal Moitrel (FDTC, 2006)

A 100dB dynamic range CMOS image sensor with global shutter. - Estelle Labonne; Gilles Sicard; Marc Renaudin; Pierre-Damien Berger (ICECS, 2006)

Practical Evaluation of Fault Countermeasures on an Asynchronous DES Crypto Processor. - Yannick Monnet; Marc Renaudin; Régis Leveugle; Nathalie Feyt; Pascal Moitrel; F. M'Buwa Nzenguet (IOLTS, 2006)

Asynchronous Design: Fault Robustness and Security Characteristics. - Marc Renaudin; Yannick Monnet (IOLTS, 2006)

QDI Latches Characteristics and Asynchronous Linear-Pipeline Performance Analysis. - Eslam Yahya; Marc Renaudin (PATMOS, 2006)

State-holding in Look-Up Tables: application to asynchronous logic. - Laurent Fesquet; Bertrand Folco; Mathieu Steiner; Marc Renaudin (VLSI-SoC, 2006)

Security evaluation of dual rail logic against DPA attacks. - Alin Razafindraibe; Philippe Maurine; Michel Robert; Marc Renaudin (VLSI-SoC, 2006)

On the Use of Feedback Systems to Dynamically Control the Supply Voltage of Low-Power Circuits. - David Rios-Arambula; Aurélien Buhrig; Gilles Sicard; Marc Renaudin (J. Low Power Electron., 2006)

Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic. - Yannick Monnet; Marc Renaudin; Régis Leveugle (IEEE Trans. Computers, 2006)

An on-pixel FPN reduction method for a high dynamic range CMO S imager. - Estelle Labonne; Gilles Sicard; Marc Renaudin (ESSCIRC, 2007)

Computationally efficient adaptive rate sampling and filtering. - Saeed Mian Qaisar; Laurent Fesquet; Marc Renaudin (EUSIPCO, 2007)

Timed Asynchronous Circuits Modeling using SystemC. - Cedric Koch-Hofer; Marc Renaudin (FDL, 2007)

A Novel Asynchronous e-FPGA Architecture for Security Applications. - Taha Beyrouthy; Alin Razafindraibe; Laurent Fesquet; Marc Renaudin; Sumanta Chaudhuri; Sylvain Guilley; Jean-Luc Danger; Philippe Hoogvorst (FPT, 2007)

Adaptive Rate Filtering Fora Signal Driven Sampling Scheme. - Saeed Mian Qaisar; Laurent Fesquet; Marc Renaudin (ICASSP (3), 2007)

Performance Modeling and Analysis of Asynchronous Linear-Pipeline with Time Variable Delays. - Eslam Yahya; Marc Renaudin (ICECS, 2007)

Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs. - Yannick Monnet; Marc Renaudin; Régis Leveugle (IOLTS, 2007)

ASC, a SystemC Extension for Modeling Asynchronous Systems, and Its Application to an Asynchronous NoC. - Cedric Koch-Hofer; Marc Renaudin; Yvain Thonnart; Pascal Vivet (NOCS, 2007)

A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling. - Sylvain Miermont; Pascal Vivet; Marc Renaudin (PATMOS, 2007)

The ARESA Project: Facilitating Research, Development and Commercialization of WSNs. - Mischa Dohler; Dominique Barthel; Florence Maraninchi; Laurent Mounier; Stephane Aubert; Christophe Dugas; Aurélien Buhrig; Franck Paugnat; Marc Renaudin; Andrzej Duda; Martin Heusse; Fabrice Valois (SECON, 2007)

A new analytical approach of the impact of jitter on continuous time delta sigma converters. - Julien Goulier; Eric André; Marc Renaudin (VLSI-SoC (Selected Papers), 2007)

Parallel Asynchronous Watershed Algorithm-Architecture. - Bruno Galilée; Franck Mamalet; Marc Renaudin; Pierre-Yves Coulon (IEEE Trans. Parallel Distributed Syst., 2007)

Estimation rapide du couple énergie/délai des circuits asynchrones QDI. - J. Fragoso; Gilles Sicard; Marc Renaudin (Tech. Sci. Informatiques, 2007)

Physical Design of FPGA Interconnect to Prevent Information Leakage. - Sumanta Chaudhuri; Sylvain Guilley; Philippe Hoogvorst; Jean-Luc Danger; Taha Beyrouthy; Alin Razafindraibe; Laurent Fesquet; Marc Renaudin (ARC, 2008)

High-Level Time-Accurate Model for the Design of Self-Timed Ring Oscillators. - Jérémie Hamon; Laurent Fesquet; Benoit Miscopein; Marc Renaudin (ASYNC, 2008)

Asynchronous Linear Pipelines: An efficient-optimal pipelining algorithm. - Eslam Yahya; Marc Renaudin (ICECS, 2008)

Detailed Analyses of Single Laser Shot Effects in the Configuration of a Virtex-II FPGA. - Gaetan Canivet; Jessy Clédière; Jean Baptiste Ferron; Frédéric Valette; Marc Renaudin; Régis Leveugle (IOLTS, 2008)

An Adaptive Resolution Computationally Efficient Short-Time Fourier Transform. - Saeed Mian Qaisar; Laurent Fesquet; Marc Renaudin (J. Electr. Comput. Eng., 2008)

Programmable/Stoppable Oscillator Based on Self-Timed Rings. - Eslam Yahya; Oussama Elissati; Hatem Zakaria; Laurent Fesquet; Marc Renaudin (ASYNC, 2009)

Comparing transient-fault effects on synchronous and on asynchronous circuits. - Rodrigo Possamai Bastos; Yannick Monnet; Gilles Sicard; Fernanda Lima Kastensmidt; Marc Renaudin; Ricardo Reis 001 (IOLTS, 2009)

A 45nm CMOS 0.35v-optimized standard cell library for ultra-low power applications. - Fady Abouzeid; Sylvain Clerc; Fabian Firmin; Marc Renaudin; Gilles Sicard (ISLPED, 2009)

Characterization of Effective Laser Spots during Attacks in the Configuration of a Virtex-II FPGA. - Gaetan Canivet; Régis Leveugle; Jessy Clédière; Frédéric Valette; Marc Renaudin (VTS, 2009)

Adaptive Rate Sampling and Filtering Based on Level Crossing Sampling. - Saeed Mian Qaisar; Laurent Fesquet; Marc Renaudin (EURASIP J. Adv. Signal Process., 2009)

Constrained Asynchronous Ring Structures for Robust Digital Oscillators. - Jérémie Hamon; Laurent Fesquet; Benoit Miscopein; Marc Renaudin (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Dependability analysis of a countermeasure against fault attacks by means of laser shots onto a SRAM-based FPGA. - Gaetan Canivet; Paolo Maistri; Régis Leveugle; Frédéric Valette; Jessy Clédière; Marc Renaudin (ASAP, 2010)

Robustness evaluation and improvements under laser-based fault attacks of an AES crypto-processor implemented on a SRAM-based FPGA. - Gaetan Canivet; P. Maistn; Régis Leveugle; Frédéric Valette; Jessy Clédière; Marc Renaudin (ETS, 2010)

Evaluating transient-fault effects on traditional C-element's implementations. - Rodrigo Possamai Bastos; Gilles Sicard; Fernanda Lima Kastensmidt; Marc Renaudin; Ricardo Reis 001 (IOLTS, 2010)

ASTEC: Asynchronous Technology for Low Power and Secured Embedded Systems. - Marc Renaudin (PATMOS, 2010)

Asynchronous circuits as alternative for mitigation of long-duration transient faults in deep-submicron technologies. - Rodrigo Possamai Bastos; Gilles Sicard; Fernanda Lima Kastensmidt; Marc Renaudin; Ricardo Reis 001 (Microelectron. Reliab., 2010)

A Secure Asynchronous FPGA Architecture, Experimental Results and Some Debug Feedback - Sumanta Chaudhuri; Sylvain Guilley; Philippe Hoogvorst; Jean-Luc Danger; Taha Beyrouthy; Alin Razafindraibe; Laurent Fesquet; Marc Renaudin (CoRR, 2011)

Glitch and Laser Fault Attacks onto a Secure AES Implementation on a SRAM-Based FPGA. - Gaetan Canivet; Paolo Maistri; Régis Leveugle; Jessy Clédière; Florent Valette; Marc Renaudin (J. Cryptol., 2011)

40nm CMOS 0.35V-Optimized Standard Cell Libraries for Ultra-Low Power Applications. - Fady Abouzeid; Sylvain Clerc; Fabian Firmin; Marc Renaudin; Tiempo Sas; Gilles Sicard (ACM Trans. Design Autom. Electr. Syst., 2011)

Tiempo Asynchronous Circuits System Verilog Modeling Language. - Marc Renaudin; Alain Fonkoua (ASYNC, 2012)

Statistical Static Timing Analysis of Conditional Asynchronous Circuits Using Model-Based Simulation. - Eslam Yahya; Laurent Fesquet; Yehea I. Ismail; Marc Renaudin (ASYNC, 2013)

Advances in asynchronous logic: from principles to GALS & NoC, recent industry applications, and commercial CAD tools. - Alex Yakovlev; Pascal Vivet; Marc Renaudin (DATE, 2013)

Clockless Design Performance Monitoring for Nanometer Technologies. - Marc Renaudin; Aurélien Buhrig; Charles Guillemet; Robin Wilson; Sylvain Engels (ASYNC, 2014)

Adaptive rate filtering a computationally efficient signal processing approach. - Saeed Mian Qaisar; Laurent Fesquet; Marc Renaudin (Signal Process., 2014)

Model-Checking Synthesizable SystemVerilog Descriptions of Asynchronous Circuits. - Aymane Bouzafour; Marc Renaudin; Hubert Garavel; Radu Mateescu 001; Wendelin Serwe (ASYNC, 2018)

A 6-Wire Plug and Play Clockless Distributed On-Chip-Sensor Network in 28 nm UTBB FD-SOI. - Marc Renaudin; Aymane Bouzafour; Sylvain Engels; Robin Wilson (J. Low Power Electron., 2018)

Modeling an Asynchronous Circuit Dedicated to the Protection Against Physical Attacks. - Radu Mateescu 001; Wendelin Serwe; Aymane Bouzafour; Marc Renaudin (MARS@ETAPS, 2020)