Half-rate GSM vocoder implementation on a dual mac digital signal processor. - Mohit K. Prasad; Paul D'Arcy; Arup Gupta; Marc S. Diamondstein; Hosahalli R. Srinivas (ICASSP, 1997)

VLSI Implementation of a 300-MHz 0.35 um CMOS 32-bit Auto-Reloadable Binary Synchronous Counter with Optimal Test Overhead Delay. - S. K. Misra; R. K. Kolagotla; Hosahalli R. Srinivas; J. C. Mo; Marc S. Diamondstein (VLSI Design, 1998)