The implementation and application of micro rollback in fault-tolerant VLSI systems. - Yuval Tamir; Marc Tremblay; David A. Rennels (FTCS, 1988)

MAR: an integrated system for focal plane edge tracking with parallel analog processing and built-in primitives for image acquisition and analysis. - Marc Tremblay; Denis Poussart (ICPR (2), 1990)

High-Performance Fault-Tolerant VLSI Systems Using Micro Rollback. - Yuval Tamir; Marc Tremblay (IEEE Trans. Computers, 1990)

The UCLA Mirror Processor: A Building Block for Self-Checking Self-Repring Computing Nodes. - Yuval Tamir; Mike Liang; Titus Lai; Marc Tremblay (FTCS, 1991)

Vlsi Implementation of focal plane Processing for Smart Vision Sensing. - Denis Poussart; Marc Tremblay; Abdel Djemouai (Pattern Recognition: Architectures, Algorithms and Applications, 1991)

A VLSI Implementation Of A Light Sensor With Imbedded Focal Plane Processing Capabilities. - Florent Parent; Marc Tremblay; Denis Laurendeau; Denis Poussart (IROS, 1992)

Focal-plane VLSI processing for multiresolution edge extraction. - Marc Tremblay; Denis Poussart (Visual Information Processing, 1992)

High resolution smart image sensor with integrated parallel analog processing for multiresolution edge extraction. - Marc Tremblay; Denis Laurendeau; Denis Poussart (Robotics Auton. Syst., 1993)

Medium level scene representation using a VLSI smart hexagonal sensor with multiresolution edge extraction capability and scale space integration processing. - Marc Tremblay; Martin Savard; Denis Poussart (CVPR, 1994)

UltraSPARC: The Next Generation Superscalar 64-bit SPARC. - Dale Greenley; J. Bauman; D. Chang; Dennis Chen; R. Eltejaein; Philip A. Ferolito; P. Fu; Robert B. Garner; D. Greenhill; H. Grewal; Kalon Holdbrook; B. Kim; et al. (COMPCON, 1995)

The Visual Instruction Set (VIS) in UltraSPARC. - Leslie Kohn; Guillermo Maturana; Marc Tremblay; A. Prabhu; Gregory B. Zyner (COMPCON, 1995)

A Fast and Flexible Performance Simulator for Micro-Architecture Trade-off Analysis on UltraSPARC-I. - Marc Tremblay; Guillermo Maturana; Atsushi Inoue; Leslie Kohn (DAC, 1995)

A three dimensional register file for superscalar processors. - Marc Tremblay; Bill Joy 001; Ken Shin (HICSS (1), 1995)

The design of the microarchitecture of UltraSPARC-I. - Marc Tremblay; Dale Greenley; Kevin Normoyle (Proc. IEEE, 1995)

A 64-b microprocessor with multimedia support. - Lavi Lev; Andy Charnas; Marc Tremblay; Alexander Dalal; Bruce A. Frederick; Chakra R. Srivatsa; David Greenhill; Dennis L. Wendell; Duy Dinh Pham; Eric Anderson; Hemraj K. Hingarh; Inayat Razzack; et al. (IEEE J. Solid State Circuits, 1995)

UltraSparc I: a four-issue processor supporting multimedia. - Marc Tremblay; J. Michael O'Connor (IEEE Micro, 1996)

VIS speeds new media processing. - Marc Tremblay; J. Michael O'Connor; Venkatesh Narayanan; Liang He (IEEE Micro, 1996)

A Focal Plane Architecture for Motion Computation. - Miguel O. Arias-Estrada; Marc Tremblay; Denis Poussart (Real Time Imaging, 1996)

picoJava-I: the Java virtual machine in hardware. - J. Michael O'Connor; Marc Tremblay (IEEE Micro, 1997)

Mixed-signal VLSI Architecture for Real-Time Computer Vision. - Stéphane Dallaire; Marc Tremblay; Denis Poussart (Real Time Imaging, 1997)

Challenges and Trends in Processor Design. - Janet Wilson; Marc Tremblay; Greg Grohoski; Brad Burgess; Earl Killian; Robert P. Colwell; Paul I. Rubinfeld (Computer, 1998)

The MAJC Architecture: A Synthesis of Parallelism and Scalability. - Marc Tremblay; Jeffrey Chan; Shailender Chaudhry; Andrew W. Conigliaro; Shing Sheung Tse (IEEE Micro, 2000)

The first MAJC microprocessor: a dual CPU system-on-a-chip. - Andre Kowalczyk; Victor Adler; Chaim Amir; Frank Chiu; Choon Ping Chng; Willem J. de Lange; Yuefei Ge; Subhendra Ghosh; Tan Canh Hoang; Baoqing Huang; Shree Kant; Y. S. Kao; et al. (IEEE J. Solid State Circuits, 2001)

Guest Editors' Introduction: Hot Chips 12. - William J. Dally; Marc Tremblay; Allen J. Baum (IEEE Micro, 2001)

High-Performance Throughput Computing. - Shailender Chaudhry; Paul Caprioli; Sherman Yip; Marc Tremblay (IEEE Micro, 2005)

A modern high-performance processor pipeline. - Marc Tremblay (ICS, 2006)

Transactional memory for a modern microprocessor. - Marc Tremblay (PODC, 2007)

A Third-Generation 65nm 16-Core 32-Thread Plus 32-Scout-Thread CMT SPARC® Processor. - Marc Tremblay; Shailender Chaudhry (ISSCC, 2008)

Simultaneous speculative threading: a novel pipeline architecture implemented in sun's rock processor. - Shailender Chaudhry; Robert Cypher; Magnus Ekman; Martin Karlsson; Anders Landin; Sherman Yip; Håkan Zeffer; Marc Tremblay (ISCA, 2009)

Architecture and Physical Implementation of a Third Generation 65 nm, 16 Core, 32 Thread Chip-Multithreading SPARC Processor. - Georgios K. Konstadinidis; Marc Tremblay; Shailender Chaudhry; Mamun Rashid; Peter F. Lai; Yukio Otaguro; Yannis Orginos; Sudhendra Parampalli; Mark Steigerwald; Shriram Gundala; Rambabu Pyapali; Leonard Rarick; et al. (IEEE J. Solid State Circuits, 2009)

Rock: A High-Performance Sparc CMT Processor. - Shailender Chaudhry; Robert Cypher; Magnus Ekman; Martin Karlsson; Anders Landin; Sherman Yip; Håkan Zeffer; Marc Tremblay (IEEE Micro, 2009)

Position Masking for Language Models. - Andy Wagner; Tiyasa Mitra; Mrinal Iyer; Godfrey Da Costa; Marc Tremblay (CoRR, 2020)