Efficient machine learning through evolving combined deep neural networks. - Rune Krauss; Marcel Merten; Mirco Bockholt; Saman Fröhlich; Rolf Drechsler (GECCO Companion, 2020)

A Codeword-based Compactor for On-Chip Generated Debug Data Using Two-Stage Artificial Neural Networks. - Marcel Merten; Sebastian Huhn 001; Rolf Drechsler (DFT, 2021)

ALF: a fitness-based artificial life form for evolving large-scale neural networks. - Rune Krauss; Marcel Merten; Mirco Bockholt; Rolf Drechsler (GECCO Companion, 2021)

Quality Assessment of RFET-based Logic Locking Protection Mechanisms using Formal Methods. - Marcel Merten; Sebastian Huhn 001; Rolf Drechsler (ETS, 2022)

A Hardware-based Evolutionary Algorithm with Multi-Objective Optimization Operators for On-Chip Transient Fault Detection. - Marcel Merten; Sebastian Huhn 001; Rolf Drechsler (VTS, 2022)

Design Enablement Flow for Circuits with Inherent Obfuscation based on Reconfigurable Transistors. - Jens Trommer; Niladri Bhattacharjee; Thomas Mikolajick; Sebastian Huhn 001; Marcel Merten; Mohammed E. Djeridane; Muhammad Hassan 002; Rolf Drechsler; Shubham Rai; Nima Kavand; Armin Darjani; Akash Kumar 001; et al. (DATE, 2023)

Quality Assessment of Logic Locking Mechanisms using Pseudo-Boolean Optimization Techniques. - Marcel Merten; Muhammad Hassan 002; Rolf Drechsler (DDECS, 2023)

Increasing SAT-Resilience of Logic Locking Mechanisms using Formal Methods. - Marcel Merten; Sebastian Huhn 001; Rolf Drechsler (ETS, 2023)

Scalable Neuroevolution of Ensemble Learners. - Marcel Merten; Rune Krauss; Rolf Drechsler (GECCO Companion, 2023)

Improving Virtual Prototype Driven Hardware Optimization by Merging Instruction Sequences. - Jan Zielasko; Rune Krauss; Marcel Merten; Rolf Drechsler (DDECS, 2024)