A digital compensation method canceling static and non-linear time-variant feedback DAC errors in ΣΔ analog-to-digital converters. - Marcel Runge; Friedel Gerfers (ISCAS, 2017)

Noise and non-linearity analysis of a charge-injection-cell-based 10-bit 50-MS/s SAR-ADC. - Marcel Runge; Dario Schmock; Friedel Gerfers (MWSCAS, 2017)

A 0.02-mm2 9-bit 100-MS/s Charge-Injection Cell Based SAR-ADC in 65-nm LP CMOS. - Marcel Runge; Dario Schmock; Philipp Scholz; Georg Böck; Friedel Gerfers (ESSCIRC, 2018)

Correlation Based Time-Variant DAC Error Estimation in Continuous-Time ∑Δ ADCs With Pseudo Random Noise. - Marcel Runge; Friedel Gerfers (ISCAS, 2018)

AMDAC Common-Mode Shifting Technique enabling Power Consumption Reduction in Pipeline ADCs. - Nima Lotfi; Marcel Runge; Friedel Gerfers (MWSCAS, 2018)

A Temperature and Process Corner Insensitive Design Method for Digital Circuits in 40nm CMOS. - Marcel Runge; Sebastian Linnhoff; Friedel Gerfers (MWSCAS, 2018)

Body-Bias Techniques in CMOS 22FDX® for Mixed-Signal Circuits and Systems. - Friedel Gerfers; Nima Lotfi; Enne Wittenhagen; Hossein Ghafarian; Yuan Tian 032; Marcel Runge (ICECS, 2019)

A Single-Channel 18.5 GS/s 5-bit Flash ADC using a Body-Biased Comparator Architecture in 22nm FD-SOI. - Nima Lotfi; Pedro Lehmann Ibáñez; Marcel Runge; Friedel Gerfers (ISCAS, 2019)

Optimized Zero Placement within Noise Coupling Transfer Functions for Oversampled ADCs. - Marcel Runge; Nima Lotfi; Friedel Gerfers (ISCAS, 2019)

A 64 GBaud 6-Bit Current Steering DAC With a Binary Tree Current Summing Network. - Paul Hollmann; Marcel Runge; Friedel Gerfers (ICECS, 2020)

A DAC Linearization Technique Enabling 15-Bit INL through Adaptive Body-Biasing in 22FDX. - Marcel Runge; Dario Schmock; Enne Wittenhagen; Friedel Gerfers (ISCAS, 2020)

A Sub-Sampling Beam-Forming Summation Track and Hold for Software Defined Radio. - Enne Wittenhagen; Marcel Runge; Wilhelm Keusgen; Friedel Gerfers (ISCAS, 2020)

A 18MS/s 76dB SNDR 93dB SFDR CT ΔΣ Modulator with Input Voltage Tracking 2nd-Order GmVC Filter and Shared FIR DAC in 22nm FDSOI CMOS. - Marcel Runge; Julius Edler; Tobias Kaiser; Friedel Gerfers (CICC, 2021)

A 0.9V 45MS/s CT ΔΣ Modulator with 94dB SFDR and 25.6fJ/conv. enabled by a Digital Static and ISI Calibration in 22 FDSOI CMOS. - Marcel Runge; Dario Schmock; Tobias Kaiser; Friedel Gerfers (CICC, 2021)

A Dynamic Body-Bias Linearization Technique Enabling Wide-Band GmC based Continous-Time Sigma-Delta Converters in 22 nm FD-SOI CMOS. - Julius Edler; Marcel Runge; Friedel Gerfers (MWSCAS, 2021)

Advanced Mixed Signal Concepts Exploiting the Strong Body-Bias Effect in CMOS 22FDX®. - Enne Wittenhagen; Marcel Runge; Nima Lotfi; Hossein Ghafarian; Yuan Tian 032; Friedel Gerfers (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 30-MHz BW 74.6-dB SNDR 92-dB SFDR CT ΔΣ Modulator with Active Body-Bias DAC Calibration in 22nm FDSOI CMOS. - Marcel Runge; Julius Edler; Dario Schmock; Tobias Kaiser; Friedel Gerfers (CICC, 2022)

A Calibration-Free 96.7 dB SNDR 4 MS/s CT I-SD Modulator With Single Feedback DAC. - Kai Misselwitz; Marcel Runge; Friedel Gerfers (ICECS 2022, 2022)

A 4.4 GS/s 220 MHz ΣΔ ADC with a Linearized Back-Gate Controlled GmC Filter. - Julius Edler; Marcel Runge; Sebastian Linnhoff; Friedel Gerfers (VLSI Technology and Circuits, 2023)

An 18-MS/s 76-dB SNDR Continuous-Time Δ Σ Modulator Incorporating an Input Voltage Tracking GmC Loop Filter. - Marcel Runge; Julius Edler; Tobias Kaiser; Kai Misselwitz; Friedel Gerfers (IEEE J. Solid State Circuits, 2023)