Enhancing automatic generation of VHDL descriptions from UML/MARTE models. - Marcela Leite; Cristiano D. Vasconcellos; Marco Aurélio Wehrmeister (INDIN, 2014)

Aspect-Oriented Model-Driven Engineering for FPGA/VHDL Based Embedded Real-Time Systems. - Marcela Leite; Marco Aurélio Wehrmeister (ISORC, 2014)

On Generating VHDL Descriptions from Aspect-Oriented UML/MARTE Models. - Marco Aurélio Wehrmeister; Marcela Leite (SBESC, 2014)

System-level design based on UML/MARTE for FPGA-based embedded real-time systems. - Marcela Leite; Marco Aurélio Wehrmeister (Des. Autom. Embed. Syst., 2016)