A case study on modeling shared memory access effects during performance analysis of HW/SW systems. - Marcello Lajolo; Anand Raghunathan; Sujit Dey; Luciano Lavagno; Alberto L. Sangiovanni-Vincentelli (CODES, 1998)

Software timing analysis using HW/SW cosimulation and instruction set simulator. - Jie Liu 001; Marcello Lajolo; Alberto L. Sangiovanni-Vincentelli (CODES, 1998)

Fast Instruction Cache Simulation Strategies in a Hardware/Software Co-Design Environment. - Marcello Lajolo; Luciano Lavagno; Alberto L. Sangiovanni-Vincentelli (ASP-DAC, 1999)

A compilation-based software estimation scheme for hardware/software co-simulation. - Marcello Lajolo; Mihai T. Lazarescu; Alberto L. Sangiovanni-Vincentelli (CODES, 1999)

Automatic test bench generation for simulation-based validation. - Marcello Lajolo; Luciano Lavagno; Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante (CODES, 2000)

Efficient Power Co-Estimation Techniques for System-on-Chip Design. - Marcello Lajolo; Anand Raghunathan; Sujit Dey; Luciano Lavagno (DATE, 2000)

Evaluating System Dependability in a Co-Design Framework. - Marcello Lajolo; Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante; Luciano Lavagno (DATE, 2000)

System-level test bench generation in a co-design framework. - Marcello Lajolo; Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante; Luciano Lavagno (ETW, 2000)

Behavioral-level test vector generation for system-on-chip designs. - Marcello Lajolo; Maurizio Rebaudengo; Matteo Sonza Reorda; Massimo Violante; Luciano Lavagno (HLDVT, 2000)

Compilation-based software performance estimation for system level design. - Mihai T. Lazarescu; Jwahar R. Bammi; Edwin A. Harcourt; Luciano Lavagno; Marcello Lajolo (HLDVT, 2000)

Early Power Estimation for System-on-Chip Designs. - Marcello Lajolo; Luciano Lavagno; Matteo Sonza Reorda; Massimo Violante (PATMOS, 2000)

Early Evaluation Of Bus Interconnects Dependability For System-On-Chip Designs. - Marcello Lajolo; Matteo Sonza Reorda; Massimo Violante (VLSI Design, 2001)

Bus guardians: an effective solution for online detection and correction of faults affecting system-on-chip buses. - Marcello Lajolo (IEEE Trans. Very Large Scale Integr. Syst., 2001)

On the evaluation of fairness for input queue switches. - Dirceu Cavendish; Marcello Lajolo; Hongbo Liu 005 (ICC, 2002)

On the support of minimum service rates for input queue switches. - Dirceu Cavendish; Marcello Lajolo; Hongbo Liu 005 (ICC, 2002)

Cosimulation-based power estimation for system-on-chip design. - Marcello Lajolo; Anand Raghunathan; Sujit Dey; Luciano Lavagno (IEEE Trans. Very Large Scale Integr. Syst., 2002)

A Case Study of a System Level Approach to Exploration of Queuing Management Schemes for Input Queue Packet Switches. - Chen He; Marcello Lajolo; Margarida F. Jacome (PDP, 2003)

Interface-Centric Abstraction Level for Rapid HW/SW Integration. - André C. Nácul; Marcello Lajolo; T. Givarjis (FDL, 2005)

Automatic synthesis of the Hardware/Software Interface. - Francesco Regazzoni 001; André C. Nácul; Marcello Lajolo (FDL, 2005)

SOFTENIT: a methodology for boosting the software content of system-on-chip designs. - Abhishek Mitra; Marcello Lajolo; Kanishka Lahiri (ACM Great Lakes Symposium on VLSI, 2005)

C-based Design of a Flexible Wrapper for Tiled Networks On Chip. - Subhek Garg; Marcello Lajolo (FDL, 2006)

Hardware/software partitioning of operating systems: a behavioral synthesis approach. - Sathish Chandra; Francesco Regazzoni 001; Marcello Lajolo (ACM Great Lakes Symposium on VLSI, 2006)

Hardware scheduling support in SMP architectures. - André C. Nácul; Francesco Regazzoni 001; Marcello Lajolo (DATE, 2007)

In Memoriam: Margarida F. Jacome. - Gustavo de Veciana; Marcello Lajolo; Chen He; Enrico Macii; Sachin S. Sapatnekar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Variation tolerant NoC design by means of self-calibrating links. - Simone Medardoni; Marcello Lajolo; Davide Bertozzi (DATE, 2008)