Modular architecture for a family of multilevel 256/192/128/64 Mbit 2-bit/cell 3 V-only NOR flash memory devices. - Andrea Silvagni; Stefano Zanardi; Alessandro Manstretta; Marco Scotti; Luca Crippa; Giancarlo Ragone; Giuseppe Fusillo; Giovanni Campardo; Osama Khouri; Marcello Stefanelli (ICECS, 2001)