A Simulator and Compiler Framework for Agile Hardware-Software Co-design Evaluation and Exploration. - Tyler Sorensen 001; Aninda Manocha; Esin Tureci; Marcelo Orenes-Vera; Juan L. Aragón; Margaret Martonosi (ICCAD, 2020)

MosaicSim: A Lightweight, Modular Simulator for Heterogeneous Systems. - Opeoluwa Matthews; Aninda Manocha; Davide Giri; Marcelo Orenes-Vera; Esin Tureci; Tyler Sorensen 001; Tae Jun Ham; Juan L. Aragón; Luca P. Carloni; Margaret Martonosi (ISPASS, 2020)

The MosaicSim Simulator (Full Technical Report). - Opeoluwa Matthews; Aninda Manocha; Davide Giri; Marcelo Orenes-Vera; Esin Tureci; Tyler Sorensen 001; Tae Jun Ham; Juan L. Aragón; Luca P. Carloni; Margaret Martonosi (CoRR, 2020)

AutoSVA: Democratizing Formal Verification of RTL Module Interactions. - Marcelo Orenes-Vera; Aninda Manocha; David Wentzlaff; Margaret Martonosi (DAC, 2021)

RECITE: A framework for user trajectory analysis in cultural sites. - Marcelo Orenes-Vera; Fernando Terroso-Saenz; Mercedes Valdés-Vela (J. Ambient Intell. Smart Environ., 2021)

Tiny but mighty: designing and realizing scalable latency tolerance for manycore SoCs. - Marcelo Orenes-Vera; Aninda Manocha; Jonathan Balkind; Fei Gao 016; Juan L. Aragón; David Wentzlaff; Margaret Martonosi (ISCA, 2022)

Cohort: Software-Oriented Acceleration for Heterogeneous SoCs. - Tianrui Wei; Nazerke Turtayeva; Marcelo Orenes-Vera; Omkar Lonkar; Jonathan Balkind (ASPLOS (3), 2023)

CIFER: A 12nm, 16mm2, 22-Core SoC with a 1541 LUT6/mm2 1.92 MOPS/LUT, Fully Synthesizable, CacheCoherent, Embedded FPGA. - Ting-Jung Chang; Ang Li 011; Fei Gao 016; Tuan Ta; Georgios Tziantzioulis; Yanghui Ou; Moyang Wang; Jinzheng Tu 001; Kaifeng Xu; Paul J. Jackson; August Ning; Grigory Chirkov; et al. (CICC, 2023)

DECADES: A 67mm2, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET. - Fei Gao 016; Ting-Jung Chang; Ang Li 011; Marcelo Orenes-Vera; Davide Giri; Paul J. Jackson; August Ning; Georgios Tziantzioulis; Joseph Zuckerman; Jinzheng Tu 001; Kaifeng Xu; Grigory Chirkov; et al. (CICC, 2023)

Dalorex: A Data-Local Program Execution and Architecture for Memory-bound Applications. - Marcelo Orenes-Vera; Esin Tureci; David Wentzlaff; Margaret Martonosi (HPCA, 2023)

Wafer-Scale Fast Fourier Transforms. - Marcelo Orenes-Vera; Ilya Sharapov; Robert Schreiber; Mathias Jacquelin; Philippe Vandermersch; Sharan Chetlur (ICS, 2023)

AutoCC: Automatic Discovery of Covert Channels in Time-Shared Hardware. - Marcelo Orenes-Vera; Hyunsung Yun; Nils Wistoff; Gernot Heiser; Luca Benini; David Wentzlaff; Margaret Martonosi (MICRO, 2023)

Massive Data-Centric Parallelism in the Chiplet Era. - Marcelo Orenes-Vera; Esin Tureci; David Wentzlaff; Margaret Martonosi (CoRR, 2023)

Using LLMs to Facilitate Formal Verification of RTL. - Marcelo Orenes-Vera; Margaret Martonosi; David Wentzlaff (CoRR, 2023)

DCRA: A Distributed Chiplet-based Reconfigurable Architecture for Irregular Applications. - Marcelo Orenes-Vera; Esin Tureci; Margaret Martonosi; David Wentzlaff (CoRR, 2023)

Tascade: Hardware Support for Atomic-free, Asynchronous and Efficient Reduction Trees. - Marcelo Orenes-Vera; Esin Tureci; David Wentzlaff; Margaret Martonosi (CoRR, 2023)

MuchiSim: A Simulation Framework for Design Exploration of Multi-Chip Manycore Systems. - Marcelo Orenes-Vera; Esin Tureci; Margaret Martonosi; David Wentzlaff (ISPASS, 2024)

Navigating Heterogeneity and Scalability in Modern Chip Design - Marcelo Orenes-Vera (2024)