Disjunctive Decomposition of Switching Functions Using Symmetry Information. - Malgorzata Chrzanowska-Jeske; Wei Wang; Jing Xia; Marcin Jeske (SBCCI, 2000)

Using a Distributed Rectangle Bin-Packing Approach for Core-based SoC Test Scheduling with Power Constraints. - Yu Xia; Malgorzata Chrzanowska-Jeske; Benyi Wang; Marcin Jeske (ICCAD, 2003)

Integrated floorplanning with buffer/channel insertion for bus-based designs. - Faran Rafiq; Malgorzata Chrzanowska-Jeske; Hannah Honghua Yang; Marcin Jeske; Naveed A. Sherwani (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Substrate noise-aware floorplanning for mixed-signal SOCs. - Marcin Jeske; Grzegorz Blakiewicz; Malgorzata Chrzanowska-Jeske; Benyi Wang (ISCAS (2), 2004)

Substrate noise optimization in early floorplanning for mixed signal SOCs. - Grzegorz Blakiewicz; Marcin Jeske; Malgorzata Chrzanowska-Jeske (SoCC, 2004)

Substrate noise modeling in early floorplanning of MS-SOCs. - Grzegorz Blakiewicz; Marcin Jeske; Malgorzata Chrzanowska-Jeske; Jin S. Zhang (ASP-DAC, 2005)