Area-oriented technology mapping for LUT-based logic blocks. - Marcin Kubica 002; Dariusz Kania (Int. J. Appl. Math. Comput. Sci., 2017)

Logic synthesis for FPGAs based on cutting of BDD. - Marcin Kubica 002; Adam Opara; Dariusz Kania (Microprocess. Microsystems, 2017)

Strategy of logic synthesis using MTBDD dedicated to FPGA. - Adam Opara; Marcin Kubica 002; Dariusz Kania (Integr., 2018)

A Technology Mapping of FSMs Based on a Graph of Excitations and Outputs. - Marcin Kubica 002; Dariusz Kania; Józef Kulisz (IEEE Access, 2019)

Methods of Improving Time Efficiency of Decomposition Dedicated at FPGA Structures and Using BDD in the Process of Cyber-Physical Synthesis. - Adam Opara; Marcin Kubica 002; Dariusz Kania (IEEE Access, 2019)

Technology Mapping for LUT-Based FPGA - Marcin Kubica 002; Adam Opara; Dariusz Kania (Springer, 2021)

Decomposition Approaches for Power Reduction. - Adam Opara; Marcin Kubica 002; Dariusz Kania (IEEE Access, 2023)

Technology mapping of multi-output functions leading to the reduction of dynamic power consumption in FPGAs. - Adam Opara; Marcin Kubica 002 (Int. J. Appl. Math. Comput. Sci., 2023)

Switching Activity Reduction of SOP Networks. - Marcin Kubica 002; Boleslaw Pochopien; Dariusz Kania (IEEE Access, 2024)