Analysis of Implementation Hierocrypt-3 algorithm (and its comparison to Camellia algorithm) using ALTERA devices. - Marcin Rogawski (IACR Cryptol. ePrint Arch., 2003)

Fair and Comprehensive Methodology for Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs. - Kris Gaj; Ekawat Homsirikamol; Marcin Rogawski (CHES, 2010)

ATHENa - Automated Tool for Hardware EvaluatioN: Toward Fair and Comprehensive Benchmarking of Cryptographic Hardware Using FPGAs. - Kris Gaj; Jens-Peter Kaps; Venkata Amirineni; Marcin Rogawski; Ekawat Homsirikamol; Benjamin Y. Brewster (FPL, 2010)

Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs. - Ekawat Homsirikamol; Marcin Rogawski; Kris Gaj (IACR Cryptol. ePrint Arch., 2010)

Area-Time Efficient Implementation of the Elliptic Curve Method of Factoring in Reconfigurable Hardware for Application in the Number Field Sieve. - Kris Gaj; Soonhak Kwon; Patrick Baier; Paul Kohlbrenner; Hoang Le; Mohammed Khaleeluddin; Ramakrishna Bachimanchi; Marcin Rogawski (IEEE Trans. Computers, 2010)

Throughput vs. Area Trade-offs in High-Speed Architectures of Five Round 3 SHA-3 Candidates Implemented Using Xilinx and Altera FPGAs. - Ekawat Homsirikamol; Marcin Rogawski; Kris Gaj (CHES, 2011)

Use of embedded FPGA resources in implementations of 14 round 2 SHA-3 candidates. - Rabia Shahid; Malik Umar Sharif; Marcin Rogawski; Kris Gaj (FPT, 2011)

Efficient Hardware Accelerator for IPSec Based on Partial Reconfiguration on Xilinx FPGAs. - Ahmad Salman; Marcin Rogawski; Jens-Peter Kaps (ReConFig, 2011)

Groestl Tweaks and their Effect on FPGA Results. - Marcin Rogawski; Kris Gaj (IACR Cryptol. ePrint Arch., 2011)

A High-Speed Unified Hardware Architecture for AES and the SHA-3 Candidate Grøstl. - Marcin Rogawski; Kris Gaj (DSD, 2012)

Comprehensive Evaluation of High-Speed and Medium-Speed Implementations of Five SHA-3 Finalists Using Xilinx and Altera FPGAs. - Kris Gaj; Ekawat Homsirikamol; Marcin Rogawski; Rabia Shahid; Malik Umar Sharif (IACR Cryptol. ePrint Arch., 2012)

Security margin evaluation of SHA-3 contest finalists through SAT-based attacks. - Ekawat Homsirikamol; Pawel Morawiecki; Marcin Rogawski; Marian Srebrny (IACR Cryptol. ePrint Arch., 2012)

A high-speed unified hardware architecture for 128 and 256-bit security levels of AES and the SHA-3 candidate Grøstl. - Marcin Rogawski; Kris Gaj; Ekawat Homsirikamol (Microprocess. Microsystems, 2013)

A novel modular adder for one thousand bits and more using fast carry chains of modern FPGAs. - Marcin Rogawski; Ekawat Homsirikamol; Kris Gaj (FPL, 2014)

ICEPOLE: High-speed, Hardware-oriented Authenticated Encryption. - Pawel Morawiecki; Kris Gaj; Ekawat Homsirikamol; Krystian Matusiewicz; Josef Pieprzyk; Marcin Rogawski; Marian Srebrny; Marcin Wójcik (IACR Cryptol. ePrint Arch., 2014)

Hardware-software codesign of RSA for optimal performance vs. flexibility trade-off. - Malik Umar Sharif; Rabia Shahid; Kris Gaj; Marcin Rogawski (FPL, 2016)