Efficient Parallelization of 5G-PUSCH on a Scalable RISC-V Many-Core Processor. - Marco Bertuletti; Yichao Zhang 003; Alessandro Vanelli-Coralli; Luca Benini (DATE, 2023)

Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster. - Marco Bertuletti; Samuel Riedel; Yichao Zhang 003; Alessandro Vanelli-Coralli; Luca Benini (SAMOS, 2023)

TeraPool-SDR: An 1.89TOPS 1024 RV-Cores 4MiB Shared-L1 Cluster for Next-Generation Open-Source Software-Defined Radios. - Yichao Zhang 003; Marco Bertuletti; Samuel Riedel; Matheus A. Cavalcante; Alessandro Vanelli-Coralli; Luca Benini (ACM Great Lakes Symposium on VLSI, 2024)

3D Partitioning with Pipeline Optimization for Low-Latency Memory Access in Many-Core SoCs. - Sudipta Das; Samuel Riedel; Marco Bertuletti; Luca Benini; Moritz Brunion; Julien Ryckaert; James Myers; Dwaipayan Biswas; Dragomir Milojevic (ISCAS, 2024)

A 1024 RV-Cores Shared-L1 Cluster with High Bandwidth Memory Link for Low-Latency 6G-SDR. - Yichao Zhang 003; Marco Bertuletti; Chi Zhang; Samuel Riedel; Alessandro Vanelli-Coralli; Luca Benini (CoRR, 2024)

A Dynamic Allocation Scheme for Adaptive Shared-Memory Mapping on Kilo-Core RV Clusters for Attention-Based Model Deployment. - Bowen Wang; Marco Bertuletti; Yichao Zhang 003; Victor J. B. Jung; Luca Benini (ASAP, 2025)

Quadrilatero: A RISC-V programmable matrix coprocessor for low-power edge applications. - Danilo Cammarata; Matteo Perotti; Marco Bertuletti; Angelo Garofalo; Pasquale Davide Schiavone; David Atienza; Luca Benini (CF (Companion), 2025)

TCDM Burst Access: Breaking the Bandwidth Barrier in Shared-L1 RVV Clusters Beyond 1000 FPUs. - Diyou Shen; Yichao Zhang 003; Marco Bertuletti; Luca Benini (DATE, 2025)

Optimizing Scalable Multi-Cluster Architectures for Next-Generation Wireless Sensing and Communication. - Samuel Riedel; Yichao Zhang 003; Marco Bertuletti; Luca Benini (IWASI, 2025)

Bandwidth-Latency-Thermal Co-Optimization of Interconnect-Dominated Many-Core 3D-IC. - Sudipta Das; Samuel Riedel; Mohamed Naeim; Moritz Brunion; Marco Bertuletti; Luca Benini; Julien Ryckaert; James Myers; Dwaipayan Biswas; Dragomir Milojevic (IEEE Trans. Very Large Scale Integr. Syst., 2025)

Maestro: A 302 GFLOPS/W and 19.8GFLOPS RISC-V Vector-Tensor Architecture for Wearable Ultrasound Edge Computing. - Mattia Sinigaglia; Amirhossein Kiamarzi; Marco Bertuletti; Luigi Ghionda; Mattia Orlandi; Riccardo Tedeschi; Aurora Di Giampietro; Yvan Tortorella; Luca Bertaccini; Simone Benatti; Giuseppe Tagliavini; Luca Benini; et al. (CoRR, 2025)

MemPool Flavors: Between Versatility and Specialization in a RISC-V Manycore Cluster. - Sergio Mazzola; Yichao Zhang 003; Marco Bertuletti; Diyou Shen; Luca Benini (CoRR, 2025)

TeraNoC: A Multi-Channel 32-bit Fine-Grained, Hybrid Mesh-Crossbar NoC for Efficient Scale-up of 1000+ Core Shared-L1-Memory Clusters. - Yichao Zhang 003; Zexin Fu; Tim Fischer 001; Yinrong Li; Marco Bertuletti; Luca Benini (CoRR, 2025)

A 66-Gb/s/5.5-W RISC-V Many-Core Cluster for 5G+ Software-Defined Radio Uplinks. - Marco Bertuletti; Yichao Zhang 003; Alessandro Vanelli-Coralli; Luca Benini (IEEE Trans. Very Large Scale Integr. Syst., 2025)