Fast RMWs for TSO: semantics and implementation. - Bharghava Rajaram; Vijay Nagarajan; Susmit Sarkar; Marco Elver (PLDI, 2013)

An automated and reproducible workflow for running and analyzing neural simulations using Lancet and IPython Notebook. - Jean-Luc Richard Stevens; Marco Elver; James A. Bednar (Frontiers Neuroinformatics, 2013)

TSO-CC: Consistency directed cache coherence for TSO. - Marco Elver; Vijay Nagarajan (HPCA, 2014)

RC3: Consistency Directed Cache Coherence for x86-64 with RC Extensions. - Marco Elver; Vijay Nagarajan (PACT, 2015)

McVerSi: A test generation framework for fast memory consistency verification in simulation. - Marco Elver; Vijay Nagarajan (HPCA, 2016)

C3D: Mitigating the NUMA bottleneck via coherent DRAM caches. - Cheng-Chieh Huang; Rakesh Kumar 003; Marco Elver; Boris Grot; Vijay Nagarajan (MICRO, 2016)

Memory consistency directed cache coherence protocols for scalable multiprocessors. - Marco Elver (2016)

Verification of a lazy cache coherence protocol against a weak memory model. - Christopher J. Banks; Marco Elver; Ruth Hoffmann; Susmit Sarkar; Paul B. Jackson; Vijay Nagarajan (FMCAD, 2017)

VerC3: A library for explicit state synthesis of concurrent systems. - Marco Elver; Christopher J. Banks; Paul B. Jackson; Vijay Nagarajan (DATE, 2018)

GWP-ASan: Sampling-Based Detection of Memory-Safety Bugs in Production. - Kostya Serebryany; Chris Kennelly; Mitch Phillips; Matthew Denton; Marco Elver; Alexander Potapenko; Matt Morehouse; Vlad Tsyrklevich; Christian Holler; Julian Lettner; David Kilzer; Lander Brandt (ICSE-SEIP, 2024)