Variable precision arithmetic circuits for FPGA-based multimedia processors. - Stefania Perri; Pasquale Corsonello; Maria Antonia Iachino; Marco Lanuzza; Giuseppe Cocorullo (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor. - Marco Lanuzza; Stefania Perri; Martin Margala; Pasquale Corsonello (FPL, 2005)

Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications. - Marco Lanuzza; Martin Margala; Pasquale Corsonello (ISLPED, 2005)

A high-performance fully reconfigurable FPGA-based 2D convolution processor. - Stefania Perri; Marco Lanuzza; Pasquale Corsonello; Giuseppe Cocorullo (Microprocess. Microsystems, 2005)

Progetto e realizzazione VLSI di circuiti aritmetici ottimizzati per applicazioni multimediali. - Marco Lanuzza (2005)

Low bit rate image compression core for onboard space applications. - Pasquale Corsonello; Stefania Perri; Giovanni Staino; Marco Lanuzza; Giuseppe Cocorullo (IEEE Trans. Circuits Syst. Video Technol., 2006)

A New Reconfigurable Coarse-Grain Architecture for Multimedia Applications. - Marco Lanuzza; Stefania Perri; Pasquale Corsonello; Martin Margala (AHS, 2007)

Design and Implementation of a 90nm Low bit-rate Image Compression Core. - Pasquale Corsonello; Stefania Perri; Giovanni Staino; Marco Lanuzza; Giuseppe Cocorullo (DSD, 2007)

MORA: A New Coarse-Grain Reconfigurable Array for High Throughput Multimedia Processing. - Marco Lanuzza; Stefania Perri; Pasquale Corsonello (SAMOS, 2007)

Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing. - Marco Lanuzza; Stefania Perri; Pasquale Corsonello; Martin Margala (PATMOS, 2008)

An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications. - Marco Lanuzza; Paolo Zicari; Fabio Frustaci; Stefania Perri; Pasquale Corsonello (ARC, 2009)

New performance/power/area efficient, reliable full adder design. - Sohan Purohit; Martin Margala; Marco Lanuzza; Pasquale Corsonello (ACM Great Lakes Symposium on VLSI, 2009)

A New Optimized High-Speed Low-Power Data-Driven Dynamic (D3L) 32-Bit Kogge-Stone Adder. - Fabio Frustaci; Marco Lanuzza (PATMOS, 2009)

Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath. - Sohan Purohit; Marco Lanuzza; Stefania Perri; Pasquale Corsonello; Martin Margala (VLSI Design, 2009)

Low-power split-path data-driven dynamic logic. - Fabio Frustaci; Marco Lanuzza; Paolo Zicari; Stefania Perri; Pasquale Corsonello (IET Circuits Devices Syst., 2009)

Design and Evaluation of an Energy-Delay-Area Efficient Datapath for Coarse-Grain Reconfigurable Computing Systems. - Sohan Purohit; Marco Lanuzza; Stefania Perri; Pasquale Corsonello; Martin Margala (J. Low Power Electron., 2009)

Designing High-Speed Adders in Power-Constrained Environments. - Fabio Frustaci; Marco Lanuzza; Paolo Zicari; Stefania Perri; Pasquale Corsonello (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

Impact of Random Process Variations on Different 65nm SRAM Cell Topologies. - Sumit Kansal; Marco Lanuzza; Pasquale Corsonello (ICETET, 2010)

A new low-power high-speed single-clock-cycle binary comparator. - Fabio Frustaci; Stefania Perri; Marco Lanuzza; Pasquale Corsonello (ISCAS, 2010)

Impact of Process Variations on Flip-Flops Energy and Timing Characteristics. - Marco Lanuzza; Raffaele De Rose; Fabio Frustaci; Stefania Perri; Pasquale Corsonello (ISVLSI, 2010)

Impact of Process Variations on Pulsed Flip-Flops: Yield Improving Circuit-Level Techniques and Comparative Analysis. - Marco Lanuzza; Raffaele De Rose; Fabio Frustaci; Stefania Perri; Pasquale Corsonello (PATMOS, 2010)

Design Space Exploration of Split-Path Data Driven Dynamic Full Adder. - Sohan Purohit; Marco Lanuzza; Martin Margala (J. Low Power Electron., 2010)

Exploiting Self-Reconfiguration Capability to Improve SRAM-based FPGA Robustness in Space and Avionics Applications. - Marco Lanuzza; Paolo Zicari; Fabio Frustaci; Stefania Perri; Pasquale Corsonello (ACM Trans. Reconfigurable Technol. Syst., 2010)

Energy-efficient single-clock-cycle binary comparator. - Fabio Frustaci; Stefania Perri; Marco Lanuzza; Pasquale Corsonello (Int. J. Circuit Theory Appl., 2012)

Comparative analysis of yield optimized pulsed flip-flops. - Marco Lanuzza; Raffaele De Rose; Fabio Frustaci; Stefania Perri; Pasquale Corsonello (Microelectron. Reliab., 2012)

Low-Power Level Shifter for Multi-Supply Voltage Designs. - Marco Lanuzza; Pasquale Corsonello; Stefania Perri (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

A Simple Circuit Approach to Improve Speed and Power Consumption in Pulse-Triggered Flip-Flops. - Marco Lanuzza (J. Low Power Electron., 2013)

Improving speed and power characteristics of pulse-triggered flip-flops. - Marco Lanuzza; Ramiro Taco (LASCAS, 2014)

Dynamic gate-level body biasing for subthreshold digital design. - Marco Lanuzza; Ramiro Taco; Domenico Albano (LASCAS, 2014)

Designing Dynamic Carry Skip Adders: Analysis and Comparison. - Raffaele De Rose; Marco Lanuzza; Fabio Frustaci; Sohan Purohit (Circuits Syst. Signal Process., 2014)

Gate-level body biasing technique for high-speed sub-threshold CMOS logic gates. - Pasquale Corsonello; Marco Lanuzza; Stefania Perri (Int. J. Circuit Theory Appl., 2014)

Analyzing noise robustness of wide fan-in dynamic logic gates under process variations. - Fabio Frustaci; Marco Lanuzza; Stefania Perri; Pasquale Corsonello (Int. J. Circuit Theory Appl., 2014)

Design of high-speed low-power parallel-prefix adder trees in nanometer technologies. - Stefania Perri; Marco Lanuzza; Pasquale Corsonello (Int. J. Circuit Theory Appl., 2014)

Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain. - Pasquale Corsonello; Fabio Frustaci; Marco Lanuzza; Stefania Perri (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Gate-level body biasing for subthreshold logic circuits: analytical modeling and design guidelines. - Domenico Albano; Marco Lanuzza; Ramiro Taco; Felice Crupi (Int. J. Circuit Theory Appl., 2015)

Fast and Wide Range Voltage Conversion in Multisupply Voltage Designs. - Marco Lanuzza; Pasquale Corsonello; Stefania Perri (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Ultra-Low-Voltage Self-Body Biasing Scheme and Its Application to Basic Arithmetic Circuits. - Ramiro Taco; Marco Lanuzza; Domenico Albano (VLSI Design, 2015)

Extended exploration of low granularity back biasing control in 28nm UTBB FD-SOI technology. - Ramiro Taco; Itamar Levi; Marco Lanuzza; Alexander Fish (ISCAS, 2016)

Design of a sub-1-V nanopower CMOS current reference. - Raffaele De Rose; Domenico Albano; Felice Crupi; Marco Lanuzza (ECCTD, 2017)

A variation-aware simulation framework for hybrid CMOS/spintronic circuits. - Raffaele De Rose; Marco Lanuzza; Felice Crupi; Giulio Siracusano; Riccardo Tomasello; Giovanni Finocchio; Mario Carpentieri; Massimo Alioto (ISCAS, 2017)

Evaluation of Dual Mode Logic in 28nm FD-SOI technology. - Ramiro Taco; Itamar Levi; Marco Lanuzza; Alexander Fish (ISCAS, 2017)

Impact of voltage scaling on STT-MRAMs through a variability-aware simulation framework. - Raffaele De Rose; Greta Carangelo; Marco Lanuzza; Felice Crupi; Giovanni Finocchio; Mario Carpentieri (SMACD, 2017)

Low energy/delay overhead level shifter for wide-range voltage conversion. - Marco Lanuzza; Felice Crupi; Sandro Rao; Raffaele De Rose; Giuseppe Iannaccone (Int. J. Circuit Theory Appl., 2017)

A physical unclonable function based on a 2-transistor subthreshold voltage divider. - Raffaele De Rose; Felice Crupi; Marco Lanuzza; Domenico Albano (Int. J. Circuit Theory Appl., 2017)

An Ultralow-Voltage Energy-Efficient Level Shifter. - Marco Lanuzza; Felice Crupi; Sandro Rao; Raffaele De Rose; Sebastiano Strangio; Giuseppe Iannaccone (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Design of a 3T current reference for low-voltage, low-power operation. - Raffaele De Rose; Felice Crupi; Maksym Paliy; Marco Lanuzza; Giuseppe Iannaccone (ICICDT, 2018)

Impact of the Emitter Contact Pattern in c-Si BC- BJ Solar Cells by Numerical Simulations. - Noemi Guerra; Raffaele De Rose; Marco Guevara; Paul Procel; Marco Lanuzza; Felice Crupi (RTSI, 2018)

A portable class of 3-transistor current references with low-power sub-0.5 V operation. - Felice Crupi; Raffaele De Rose; Maksym Paliy; Marco Lanuzza; Mattia Perna; Giuseppe Iannaccone (Int. J. Circuit Theory Appl., 2018)

A Variation-Aware Timing Modeling Approach for Write Operation in Hybrid CMOS/STT-MTJ Circuits. - Raffaele De Rose; Marco Lanuzza; Felice Crupi; Giulio Siracusano; Riccardo Tomasello; Giovanni Finocchio; Mario Carpentieri; Massimo Alioto (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Evaluating the Energy Efficiency of STT-MRAMs Based on Perpendicular MTJs with Double Reference Layers. - Marco Lanuzza; Raffaele De Rose; Esteban Garzón; Felice Crupi (ASICON, 2019)

Device-to-System Level Simulation Framework for STT-DMTJ Based Cache Memory. - Esteban Garzón; Raffaele De Rose; Felice Crupi; Marco Lanuzza (ICECS, 2019)

An Energy Aware Variation-Tolerant Writing Termination Control for STT-based Non Volatile Flip-Flops. - Marco Lanuzza; Raffaele De Rose; Felice Crupi; Massimo Alioto (ICECS, 2019)

Making IoT Services Accountable: A Solution Based on Blockchain and Physically Unclonable Functions. - Carmelo Felicetti; Angelo Furfaro; Domenico Saccà; Massimo Vatalaro; Marco Lanuzza; Felice Crupi (IDCS, 2019)

Live Demo: An 88fJ / 40 MHz [0.4V] - 0.61pJ / 1GHz [0.9V] Dual Mode Logic 8×8-Bit Multiplier Accumulator with a Self-Adjustment Mechanism in 28 nm FD-SOI. - Ramiro Taco; Itamar Levi; Marco Lanuzza; Alexander Fish (ISCAS, 2019)

Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs. - Esteban Garzón; Raffaele De Rose; Felice Crupi; Lionel Trojman; Giovanni Finocchio; Mario Carpentieri; Marco Lanuzza (SMACD, 2019)

Double-precision Dual Mode Logic carry-save multiplier. - Raffaele De Rose; Paul Romero; Marco Lanuzza (Integr., 2019)

An 88-fJ/40-MHz [0.4 V]-0.61-pJ/1-GHz [0.9 V] Dual-Mode Logic 8 × 8 bit Multiplier Accumulator With a Self-Adjustment Mechanism in 28-nm FD-SOI. - Ramiro Taco; Itamar Levi; Marco Lanuzza; Alexander Fish (IEEE J. Solid State Circuits, 2019)

Robust Dual Mode Pass Logic (DMPL) for Energy Efficiency and High Performance. - Inbal Stanger; Netanel Shavit; Ramiro Taco; Leonid Yavits; Marco Lanuzza; Alexander Fish (ISCAS, 2020)

Exploiting Single-Well Design for Energy-Efficient Ultra-Wide Voltage Range Dual Mode Logic-Based Digital Circuits in 28nm FD-SOI Technology. - Ramiro Taco; Leonid Yavits; Netanel Shavit; Inbal Stanger; Marco Lanuzza; Alexander Fish (ISCAS, 2020)

A 0.25-V, 5.3-pW Voltage Reference with 25-μV/°C Temperature Coefficient, 140-μV/V Line Sensitivity and 2, 200-μm2 Area in 180nm. - Luigi Fassio; Longyang Lin; Raffaele De Rose; Marco Lanuzza; Felice Crupi; Massimo Alioto (VLSI Circuits, 2020)

Assessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework. - Esteban Garzón; Raffaele De Rose; Felice Crupi; Lionel Trojman; Giovanni Finocchio; Mario Carpentieri; Marco Lanuzza (Integr., 2020)

Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths. - Inbal Stanger; Netanel Shavit; Ramiro Taco; Marco Lanuzza; Alexander Fish (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A 3.2-pW, 0.2-V Trimming-Less Voltage Reference with 1.4-mV Across-Wafer Total Accuracy. - Luigi Fassio; Longyang Lin; Raffaele De Rose; Marco Lanuzza; Felice Crupi; Massimo Alioto (ESSCIRC, 2021)

Live Demonstration: A 0.8V, 1.54 pJ / 940 MHz Dual Mode Logic-Based 16x16-Bit Booth Multiplier in 16-nm FinFET. - Netanel Shavit; Inbal Stanger; Ramiro Taco; Marco Lanuzza; Alexander Fish (ISCAS, 2021)

Live Demo: Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths. - Inbal Stanger; Netanel Shavit; Ramiro Taco; Marco Lanuzza; Alexander Fish (ISCAS, 2021)

High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator. - Ricardo Escobar; Luis-Miguel Prócel; Lionel Trojman; Marco Lanuzza; Ramiro Taco (LASCAS, 2021)

RF-DC Multiplier for RF Energy Harvester based on 32nm and TFET technologies. - Lionel Trojman; David Rivadeneira; Marco Villegas; Eliana Acurio; Marco Lanuzza; Luis-Miguel Procel; Ramiro Taco (LASCAS, 2021)

Exploiting Silicon Fingerprint for Device Authentication Using CMOS-PUF and ECC. - Carmelo Felicetti; Marco Lanuzza; Antonino Rullo; Domenico Saccà; Felice Crupi (SmartIoT, 2021)

Hamming Distance Tolerant Content-Addressable Memory (HD-CAM) for Approximate Matching Applications. - Esteban Garzón; Roman Golman; Zuher Jahshan; Robert Hanhan; Natan Vinshtok-Melnik; Marco Lanuzza; Adam Teman; Leonid Yavits (CoRR, 2021)

Trimming-Less Voltage Reference for Highly Uncertain Harvesting Down to 0.25 V, 5.4 pW. - Luigi Fassio; Longyang Lin; Raffaele De Rose; Marco Lanuzza; Felice Crupi; Massimo Alioto (IEEE J. Solid State Circuits, 2021)

A 0.6-to-1.8V CMOS Current Reference With Near-100% Power Utilization. - Luigi Fassio; Longyang Lin; Raffaele De Rose; Marco Lanuzza; Felice Crupi; Massimo Alioto (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A Robust, High-Speed and Energy-Efficient Ultralow-Voltage Level Shifter. - Luigi Fassio; Francesco Settino; Longyang Lin; Raffaele De Rose; Marco Lanuzza; Felice Crupi; Massimo Alioto (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Gain-Cell Embedded DRAM Under Cryogenic Operation - A First Study. - Esteban Garzón; Yosi Greenblatt; Odem Harel; Marco Lanuzza; Adam Teman (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Stability-Area Trade-off in Static CMOS PUF Based on 4T Subthreshold Voltage Divider. - Massimo Vatalaro; Raffaele De Rose; Marco Lanuzza; Felice Crupi (ICECS 2022, 2022)

EDAM: edit distance tolerant approximate matching content addressable memory. - Robert Hanhan; Esteban Garzón; Zuher Jahshan; Adam Teman; Marco Lanuzza; Leonid Yavits (ISCA, 2022)

A RISC-V-based Research Platform for Rapid Design Cycle. - Esteban Garzón; Roman Golman; Odem Harel; Tzachi Noy; Yehuda Kra; Asaf Pollock; Slava Yuzhaninov; Yonatan Shoshan; Yehuda Rudin; Yoav Weizman; Marco Lanuzza; Adam Teman (ISCAS, 2022)

Voltage and Technology Scaling of DMTJ-based STT-MRAMs for Energy-Efficient Embedded Memories. - Esteban Garzón; Ramiro Taco; Luis-Miguel Prócel; Lionel Trojman; Marco Lanuzza (LASCAS, 2022)

Voltage-to-Voltage Sigmoid Neuron Activation Function Design for Artificial Neural Networks. - Tatiana Moposita; Lionel Trojman; Felice Crupi; Marco Lanuzza; Andrei Vladimirescu (LASCAS, 2022)

Hamming Distance Tolerant Content-Addressable Memory (HD-CAM) for DNA Classification. - Esteban Garzón; Roman Golman; Zuher Jahshan; Robert Hanhan; Natan Vinshtok-Melnik; Marco Lanuzza; Adam Teman; Leonid Yavits (IEEE Access, 2022)

All-Analog Silicon Integration of Image Sensor and Neural Computing Engine for Image Classification. - Benjamin Zambrano; Sebastiano Strangio; Tommaso Rizzo; Esteban Garzón; Marco Lanuzza; Giuseppe Iannaccone (IEEE Access, 2022)

Adjusting Thermal Stability in Double-Barrier MTJ for Energy Improvement in Cryogenic STT-MRAMs. - Esteban Garzón; Raffaele De Rose; Felice Crupi; Lionel Trojman; Adam Teman; Marco Lanuzza (CoRR, 2022)

Smart Material Implication Using Spin-Transfer Torque Magnetic Tunnel Junctions for Logic-in-Memory Computing. - Raffaele De Rose; Tommaso Zanotti; Francesco Maria Puglisi; Felice Crupi; Paolo Pavan; Marco Lanuzza (CoRR, 2022)

A 0.6V$-$1.8V Compact Temperature Sensor with 0.24°C Resolution, $ pm$1.4°C Inaccuracy and 1.06nJ per Conversion. - Benjamin Zambrano; Esteban Garzón; Sebastiano Strangio; Giuseppe Iannaccone; Marco Lanuzza (CoRR, 2022)

Static CMOS Physically Unclonable Function Based on 4T Voltage Divider With 0.6%-1.5% Bit Instability at 0.4-1.8 V Operation in 180 nm. - Massimo Vatalaro; Raffaele De Rose; Marco Lanuzza; Felice Crupi (IEEE J. Solid State Circuits, 2022)

AIDA: Associative In-Memory Deep Learning Accelerator. - Esteban Garzón; Adam Teman; Marco Lanuzza; Leonid Yavits (IEEE Micro, 2022)

A 0.05 mm², 350 mV, 14 nW Fully-Integrated Temperature Sensor in 180-nm CMOS. - Benjamin Zambrano; Esteban Garzón; Sebastiano Strangio; Felice Crupi; Marco Lanuzza (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

STT-MRAM Technology For Energy-Efficient Cryogenic Memory Applications. - Esteban Garzón; Leonid Yavits; Adam Teman; Marco Lanuzza (LASCAS, 2023)

Voltage Reference With Corner-Aware Replica Selection/Merging for 1.4-mV Accuracy in Harvested Systems Down to 3.9 pW, 0.2 V. - Luigi Fassio; Longyang Lin; Raffaele De Rose; Marco Lanuzza; Felice Crupi; Massimo Alioto (IEEE Access, 2023)

A Low-Energy DMTJ-Based Ternary Content- Addressable Memory With Reliable Sub-Nanosecond Search Operation. - Esteban Garzón; Leonid Yavits; Giovanni Finocchio; Mario Carpentieri; Adam Teman; Marco Lanuzza (IEEE Access, 2023)

Efficient Implementation of Many-Ported Memories by Using Standard-Cell Memory Approach. - Hanan Marinberg; Esteban Garzón; Tzachi Noy; Marco Lanuzza; Adam Teman (IEEE Access, 2023)

SIMPLY+: A Reliable STT-MRAM-Based Smart Material Implication Architecture for In-Memory Computing. - Tatiana Moposita; Esteban Garzón; Raffaele De Rose; Felice Crupi; Andrei Vladimirescu; Lionel Trojman; Marco Lanuzza (IEEE Access, 2023)

AM4: MRAM Crossbar Based CAM/TCAM/ACAM/AP for In-Memory Computing. - Esteban Garzón; Marco Lanuzza; Adam Teman; Leonid Yavits (IEEE J. Emerg. Sel. Topics Circuits Syst., 2023)

Efficiency of Double-Barrier Magnetic Tunnel Junction-Based Digital eNVM Array for Neuro-Inspired Computing. - Tatiana Moposita; Esteban Garzón; Felice Crupi; Lionel Trojman; Andrei Vladimirescu; Marco Lanuzza (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

XNOR-Bitcount Operation Exploiting Computing-In-Memory With STT-MRAMs. - Ariana Musello; Esteban Garzón; Marco Lanuzza; Luis-Miguel Prócel; Ramiro Taco (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A Low-Complexity Sensing Scheme for Approximate Matching Content-Addressable Memory. - Esteban Garzón; Roman Golman; Marco Lanuzza; Adam Teman; Leonid Yavits (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

FASTA: Revisiting Fully Associative Memories in Computer Microarchitecture. - Esteban Garzón; Robert Hanhan; Marco Lanuzza; Adam Teman; Leonid Yavits (IEEE Access, 2024)

Designing Precharge-Free Energy-Efficient Content-Addressable Memories. - Ramiro Taco; Esteban Garzón; Robert Hanhan; Adam Teman; Leonid Yavits; Marco Lanuzza (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Non-Volatile Content-Addressable Memory For Energy-Efficient & High-Performance Search And Update Operations. - Alessandro Bedoya; Benjamin Zambrano; Ramiro Taco; Luis-Miguel Prócel; Marco Lanuzza; Esteban Garzón (ISCAS, 2025)

Low Matchline Voltage Swing Content-Addressable Memory Cell. - Cristhopher Mosquera; Ramiro Taco; Benjamin Zambrano; Luis-Miguel Procel; Esteban Garzón; Marco Lanuzza (ISCAS, 2025)

Towards Low-Power High-Performance Content-Addressable Memory: A Robust Precharge-Free Approach. - Ramiro Taco; Esteban Garzón; Adam Teman; Leonid Yavits; Marco Lanuzza (ISCAS, 2025)

A Multi-Bit PUF Architecture Using a 2T Sub-Threshold Voltage Divider. - Massimo Vatalaro; Raffaele De Rose; Vincenzo Maccaronio; Marco Lanuzza; Felice Crupi (ISCAS, 2025)

SpaceCAM: A 16 nm FinFET Low-Power Soft-Error Tolerant TCAM Design for Space Communication Applications. - Itay Merlin; Benjamin Zambrano; Marco Lanuzza; Alexander Fish; Avner Haran; Leonid Yavits (IEEE Access, 2025)

PUF-Based Authentication-Oriented Architecture for Identification Tags. - Antonino Rullo; Carmelo Felicetti; Massimo Vatalaro; Raffaele De Rose; Marco Lanuzza; Felice Crupi; Domenico Saccà (IEEE Trans. Dependable Secur. Comput., 2025)

Highly Stable PUFs Based on Stacked Voltage Divider for Near-Zero BER Native Sensitivity to Voltage Variations. - Massimo Vatalaro; Raffaele De Rose; Vincenzo Maccaronio; Marco Lanuzza; Felice Crupi (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A 128-kbit Approximate Search-Capable Content-Addressable Memory (CAM) With Tunable Hamming Distance. - Esteban Garzón; Eyal Rechef; Roman Golman; Odem Harel; Yuval Harary; Paz Snapir; Marco Lanuzza; Adam Teman; Leonid Yavits (IEEE J. Solid State Circuits, 2025)