Marco Lattuada

Orcid: 0000-0003-0062-6049

Affiliations:
  • Politecnico di Milano, Italy


According to our database1, Marco Lattuada authored at least 40 papers between 2007 and 2023.

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Bibliography

2023
A Path Relinking Method for the Joint Online Scheduling and Capacity Allocation of DL Training Workloads in GPU as a Service Systems.
IEEE Trans. Serv. Comput., 2023

µ-FF: On-Device Forward-Forward Training Algorithm for Microcontrollers.
Proceedings of the 2023 IEEE International Conference on Smart Computing, 2023

aMLLibrary: An AutoML Approach For Performance Prediction.
Proceedings of the 37th ECMS International Conference on Modelling and Simulation, 2023

2022
Optimal Resource Allocation of Cloud-Based Spark Applications.
IEEE Trans. Cloud Comput., 2022

Architectural Design of Cloud Applications: A Performance-Aware Cost Minimization Approach.
IEEE Trans. Cloud Comput., 2022

Svelto: High-Level Synthesis of Multi-Threaded Accelerators for Graph Analytics.
IEEE Trans. Computers, 2022

Performance prediction of deep learning applications training in GPU as a service systems.
Clust. Comput., 2022

Neural keypoint detection for visual gestures on micro-controllers.
Proceedings of the IEEE International Conference on Metrology for Extended Reality, 2022

2021
Comparing Industry Frameworks with Deeply Quantized Neural Networks on Microcontrollers.
Proceedings of the IEEE International Conference on Consumer Electronics, 2021

ANDREAS: Artificial intelligence traiNing scheDuler foR accElerAted resource clusterS.
Proceedings of the 8th International Conference on Future Internet of Things and Cloud, 2021

Invited: Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
Hierarchical Scheduling in on-demand GPU-as-a-Service Systems.
Proceedings of the 22nd International Symposium on Symbolic and Numeric Algorithms for Scientific Computing, 2020

2019
A Design Flow Engine for the Support of Customized Dynamic High Level Synthesis Flows.
ACM Trans. Reconfigurable Technol. Syst., 2019

BIGSEA: A Big Data analytics platform for public transportation information.
Future Gener. Comput. Syst., 2019

Optimizing on-demand GPUs in the Cloud for Deep Learning Applications Training.
Proceedings of the 2019 4th International Conference on Computing, 2019

Gray-Box Models for Performance Assessment of Spark Applications.
Proceedings of the 9th International Conference on Cloud Computing and Services Science, 2019

Software defined architectures for data analytics.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Machine Learning for Performance Prediction of Spark Cloud Applications.
Proceedings of the 12th IEEE International Conference on Cloud Computing, 2019

2018
Data Transfers Analysis in Computer Assisted Design Flow of FPGA Accelerators for Aerospace Systems.
IEEE Trans. Multi Scale Comput. Syst., 2018

2017
Using Efficient Path Profiling to Optimize Memory Consumption of On-Chip Debugging for High-Level Synthesis.
ACM Trans. Embed. Comput. Syst., 2017

Exploiting vectorization in high level synthesis of nested irregular loops.
J. Syst. Archit., 2017

2016
Performance Estimation of Task Graphs Based on Path Profiling.
Int. J. Parallel Program., 2016

Efficient synthesis of graph methods: a dynamically scheduled architecture.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

A dynamically scheduled architecture for the synthesis of graph methods.
Proceedings of the 2016 IEEE Hot Chips 28 Symposium (HCS), 2016

A Dynamically Scheduled Architecture for the Synthesis of Graph Database Queries.
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

Enabling the high level synthesis of data analytics accelerators.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

2015
Modeling Resolution of Resources Contention in Synchronous Data Flow Graphs.
J. Signal Process. Syst., 2015

Code Transformations Based on Speculative SDC Scheduling.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

High Level Synthesis of RDF Queries for Graph Analytics.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Exploiting Outer Loops Vectorization in High Level Synthesis.
Proceedings of the Architecture of Computing Systems - ARCS 2015, 2015

2013
Modeling pipelined application with Synchronous Data Flow graphs.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

2012
Performance estimation of embedded software with confidence levels.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2010
A methodology for performance estimation of heterogeneous multiprocessors embedded systems.
PhD thesis, 2010

HArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms.
IEEE Micro, 2010

Fine grain analysis of simulators accuracy for calibrating performance models.
Proceedings of the 21st IEEE International Symposium on Rapid System Prototyping, 2010

Performance modeling of embedded applications with zero architectural knowledge.
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

Combining Target-independent Analysis with Dynamic Profiling to Build the Performance Model of a DSP.
Proceedings of the 10th IEEE International Conference on Computer and Information Technology, 2010

2009
Performance estimation for task graphs combining sequential path profiling and control dependence regions.
Proceedings of the 7th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2009), 2009

Performance modeling of parallel applications on MPSoCs.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009

2007
Automatic Parallelization of Sequential Specifications for Symmetric MPSoCs.
Proceedings of the Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30, 2007


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