Marco Lattuada

According to our database1, Marco Lattuada authored at least 24 papers between 2007 and 2019.

Collaborative distances:



In proceedings 
PhD thesis 





BIGSEA: A Big Data analytics platform for public transportation information.
Future Generation Comp. Syst., 2019

Gray-Box Models for Performance Assessment of Spark Applications.
Proceedings of the 9th International Conference on Cloud Computing and Services Science, 2019

Software defined architectures for data analytics.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Data Transfers Analysis in Computer Assisted Design Flow of FPGA Accelerators for Aerospace Systems.
IEEE Trans. Multi-Scale Computing Systems, 2018

Dynamic DNA Damage and Repair Modeling: Bridging the Gap Between Experimental Damage Readout and Model Structure.
Proceedings of the Artificial Life and Evolutionary Computation - 13th Italian Workshop, 2018

Using Efficient Path Profiling to Optimize Memory Consumption of On-Chip Debugging for High-Level Synthesis.
ACM Trans. Embedded Comput. Syst., 2017

Exploiting vectorization in high level synthesis of nested irregular loops.
Journal of Systems Architecture - Embedded Systems Design, 2017

Performance Estimation of Task Graphs Based on Path Profiling.
International Journal of Parallel Programming, 2016

Efficient synthesis of graph methods: a dynamically scheduled architecture.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

A dynamically scheduled architecture for the synthesis of graph methods.
Proceedings of the 2016 IEEE Hot Chips 28 Symposium (HCS), 2016

A Dynamically Scheduled Architecture for the Synthesis of Graph Database Queries.
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

Enabling the high level synthesis of data analytics accelerators.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

Modeling Resolution of Resources Contention in Synchronous Data Flow Graphs.
Signal Processing Systems, 2015

Code Transformations Based on Speculative SDC Scheduling.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

High Level Synthesis of RDF Queries for Graph Analytics.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Exploiting Outer Loops Vectorization in High Level Synthesis.
Proceedings of the Architecture of Computing Systems - ARCS 2015, 2015

Modeling pipelined application with Synchronous Data Flow graphs.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

Performance estimation of embedded software with confidence levels.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

HArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms.
IEEE Micro, 2010

Fine grain analysis of simulators accuracy for calibrating performance models.
Proceedings of the 21st IEEE International Symposium on Rapid System Prototyping, 2010

Performance modeling of embedded applications with zero architectural knowledge.
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

Combining Target-independent Analysis with Dynamic Profiling to Build the Performance Model of a DSP.
Proceedings of the 10th IEEE International Conference on Computer and Information Technology, 2010

Performance estimation for task graphs combining sequential path profiling and control dependence regions.
Proceedings of the 7th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2009), 2009

Automatic Parallelization of Sequential Specifications for Symmetric MPSoCs.
Proceedings of the Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30, 2007