Analysis and Simulation of a PLL Architecture Towards a Fully Integrated 65 nm Solution for the New Spacefibre Standard. - Marco Mestice; Bruno Neri; Sergio Saponara (ApplePies, 2019)

Analysis and Design of Integrated Blocks for a 6.25 GHz Spacefibre PLL. - Marco Mestice; Bruno Neri; Gabriele Ciarpi; Sergio Saponara (Sensors, 2020)

A 2 GHz Wide Tuning Range LC-Tank Digitally Controlled Oscillator in 28 nm CMOS Technology. - Gabriele Ciarpi; G. Puccioni; Marco Mestice; Danilo Monda; Daniele Rossi 001; Sergio Saponara (ApplePies, 2022)

A Low-Area, Low-Power, Wide Tuning Range Digitally Controlled Oscillator for Power Management Systems in 28 nm CMOS Technology. - Marco Mestice; G. Biondi; Gabriele Ciarpi; Daniele Rossi 001; Sergio Saponara (ApplePies, 2022)

Wire Bonding: Limitations and Opportunities for High-Speed Serial Communications. - Gabriele Ciarpi; Marco Mestice; Daniele Rossi 001; Sergio Saponara (ApplePies, 2023)

Smart Kinetic Floor System for Energy Harvesting and Data Acquisition in High Foot-Traffic Areas. - Gabriele Ciarpi; Ettore Noccetti; Luca Ceragioli; Marco Mestice; Daniele Rossi 001; Sergio Saponara (ApplePies, 2023)

10 Gb/s Line Driver in 65 nm CMOS Technology for Radiation Environments. - Gabriele Ciarpi; Marco Mestice; Daniele Rossi 001; Fabrizio Palla; Sergio Saponara (ICECS, 2023)

A 10 Gb/s Line Driver in 65 nm CMOS Technology for Radiation-Pervaded and High-Temperature Applications. - Gabriele Ciarpi; Marco Mestice; Daniele Rossi 001; Fabrizio Palla; Sergio Saponara (IEEE Access, 2023)

An Area-Oriented Approach to the System-Level Design of Charge-Pump Phase-Locked Loops. - Marco Mestice; Gabriele Ciarpi; Daniele Rossi 001; Sergio Saponara (ApplePies, 2024)

Design and Experimental Verification of a 6.25-GHz PLL for Harsh Temperature Conditions in 65-nm CMOS Technology. - Marco Mestice; Gabriele Ciarpi; Daniele Rossi 001; Sergio Saponara (IEEE Trans. Instrum. Meas., 2024)