A Special-purpose Coprocessor for Qualitative Simulation. - Gerald Friedl; Marco Platzner; Bernhard Rinner (Euro-Par, 1995)

A distributed computer architecture for qualitative simulation based on a multi-DSP and FPGAs. - Marco Platzner; Bernhard Rinner; Reinhold Weiss (PDP, 1995)

Exploiting Parallelism in Constraint Satisfaction for Qualitative Simulation. - Marco Platzner; Bernhard Rinner; Reinhold Weiss (J. Univers. Comput. Sci., 1995)

Parallel qualitative simulation. - Marco Platzner; Bernhard Rinner; Reinhold Weiss (Simul. Pract. Theory, 1997)

Acceleration of Satisfiability Algorithms by Reconfigurable Hardware. - Marco Platzner; Giovanni De Micheli (FPL, 1998)

Communication Synthesis for Reconfigurable Embedded Systems. - Michael Eisenring; Marco Platzner; Lothar Thiele (FPL, 1999)

Dynamic Circuit Generation for Boolean Satisfiability in an Object-Oriented Design Environment. - Oskar Mencer; Marco Platzner (HICSS, 1999)

Optimization of Run-Time Reconfigurable Embedded Systems. - Michael Eisenring; Marco Platzner (FPL, 2000)

An Implementation Framework for Run-time Reconfigurable Systems. - Michael Eisenring; Marco Platzner (PDPTA, 2000)

Reconfigurable Accelerators for Combinatorial Problems. - Marco Platzner (Computer, 2000)

Toward Embedded Qualitative Simulation: A Specialized Computer Architecture for QSim. - Marco Platzner; Bernhard Rinner; Reinhold Weiss (IEEE Intell. Syst., 2000)

Object-oriented domain specific compilers for programming FPGAs. - Oskar Mencer; Marco Platzner; Martin Morf; Michael J. Flynn (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Custom Computing Machines for the Set Covering Problem. - Christian Plessl; Marco Platzner (FCCM, 2002)

Partially Reconfigurable Cores for Xilinx Virtex. - Matthias Dyer; Christian Plessl; Marco Platzner (FPL, 2002)

Reconfigurable Hardware in Wearable Computing Nodes. - Christian Plessl; Rolf Enzler; Herbert Walder; Jan Beutel; Marco Platzner; Lothar Thiele (ISWC, 2002)

A Framework for Run-time Reconfigurable Systems. - Michael Eisenring; Marco Platzner (J. Supercomput., 2002)

Online Scheduling for Block-Partitioned Reconfigurable Devices . - Herbert Walder; Marco Platzner (DATE, 2003)

Co-Simulation of a Hybrid Multi-Context Architecture. - Rolf Enzler; Christian Plessl; Marco Platzner (Engineering of Reconfigurable Systems and Algorithms, 2003)

Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations. - Herbert Walder; Marco Platzner (Engineering of Reconfigurable Systems and Algorithms, 2003)

Virtualizing Hardware with Multi-context Reconfigurable Arrays. - Rolf Enzler; Christian Plessl; Marco Platzner (FPL, 2003)

Heuristics for Onine Scheduling Real-Time Tasks to Partially Reconfigurable Devices. - Christoph Steiger; Herbert Walder; Marco Platzner (FPL, 2003)

TKDM - a reconfigurable co-processor in a PC's memory slot. - Christian Plessl; Marco Platzner (FPT, 2003)

Fast Online Task Placement on FPGAs: Free Space Partitioning and 2D-Hashing. - Herbert Walder; Christoph Steiger; Marco Platzner (IPDPS, 2003)

Online Scheduling and Placement of Real-time Tasks to Partially Reconfigurable Devices. - Christoph Steiger; Herbert Walder; Marco Platzner; Lothar Thiele (RTSS, 2003)

The case for reconfigurable hardware in wearable computing. - Christian Plessl; Rolf Enzler; Herbert Walder; Jan Beutel; Marco Platzner; Lothar Thiele; Gerhard Tröster (Pers. Ubiquitous Comput., 2003)

Instance-Specific Accelerators for Minimum Covering. - Christian Plessl; Marco Platzner (J. Supercomput., 2003)

Virtualization of Hardware - Introduction and Survey. - Christian Plessl; Marco Platzner (ERSA, 2004)

XF-Board: A Prototyping Platform for Reconfigurable Hardware Operating Systems. - Herbert Walder; Samuel Nobs; Marco Platzner (ERSA, 2004)

Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine. - Matthias Dyer; Marco Platzner; Lothar Thiele (FCCM, 2004)

A Runtime Environment for Reconfigurable Hardware Operating Systems. - Herbert Walder; Marco Platzner (FPL, 2004)

Operating Systems for Reconfigurable Embedded Platforms: Online Scheduling of Real-Time Tasks. - Christoph Steiger; Herbert Walder; Marco Platzner (IEEE Trans. Computers, 2004)

Zippy - A coarse-grained reconfigurable array with support for hardware virtualization. - Christian Plessl; Marco Platzner (ASAP, 2005)

A Heuristic Approach to Schedule Periodic Real-Time Tasks on Reconfigurable Hardware. - Klaus Danne; Marco Platzner (FPL, 2005)

Periodic Real-Time Scheduling for FPGA Computers. - Klaus Danne; Marco Platzner (WISES, 2005)

System-level performance evaluation of reconfigurable processors. - Rolf Enzler; Christian Plessl; Marco Platzner (Microprocess. Microsystems, 2005)

Executing Hardware Tasks on Dynamically Reconfigurable Devices Under Real-Time Conditions. - Klaus Danne; Roland Mühlenbernd; Marco Platzner (FPL, 2006)

Optimal temporal partitioning based on slowdown and retiming. - Christian Plessl; Marco Platzner; Lothar Thiele (FPT, 2006)

Partitioned scheduling of periodic real-time tasks onto reconfigurable hardware. - Klaus Danne; Marco Platzner (IPDPS, 2006)

An EDF schedulability test for periodic tasks on reconfigurable hardware devices. - Klaus Danne; Marco Platzner (LCTES, 2006)

MOVES: A Modular Framework for Hardware Evolution. - Paul Kaufmann; Marco Platzner (AHS, 2007)

Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution. - Paul Kaufmann; Marco Platzner (ARCS, 2007)

A Many-core Implementation based on the Reconfigurable Mesh Model. - Heiner Giefers; Marco Platzner (FPL, 2007)

ReconOS: An RTOS supporting Hard- and Software Threads. - Enno Lübbers; Marco Platzner (FPL, 2007)

Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster. - Tobias Schumacher 001; Enno Lübbers; Paul Kaufmann; Marco Platzner (PARCO, 2007)

Dynamically Reconfigurable Architectures. - Neil Bergmann; Marco Platzner; Jürgen Teich (EURASIP J. Embed. Syst., 2007)

Server-based execution of periodic tasks on dynamically reconfigurable hardware. - Klaus Danne; Roland Mühlenbernd; Marco Platzner (IET Comput. Digit. Tech., 2007)

Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control. - Kyrre Glette; Jim Tørresen; Thiemo Gruber; Bernhard Sick; Paul Kaufmann; Marco Platzner (AHS, 2008)

Communication and Synchronization in Multithreaded Reconfigurable Computing Systems. - Enno Lübbers; Marco Platzner (ERSA, 2008)

The GOmputer: Accelerating GO with FPGAs. - Marco Platzner; Sven Döhre; Markus Happe; Tobias Kenter; Ulf Lorenz; Tobias Schumacher 001; Andre Send; Alexander Warkentin (ERSA, 2008)

A Hardware Accelerator for k-th Nearest Neighbor Thinning. - Tobias Schumacher 001; Robert Meiche; Paul Kaufmann; Enno Lübbers; Christian Plessl; Marco Platzner (ERSA, 2008)

Fine grain reconfigurable architectures. - Josef Angermeier; Mateusz Majer; Jürgen Teich; Lars Braun; Tobias Schwalb; Philipp Graf; Michael Hübner 001; Jürgen Becker 001; Enno Lübbers; Marco Platzner; Christopher Claus; Walter Stechele; et al. (FPL, 2008)

A portable abstraction layer for hardware threads. - Enno Lübbers; Marco Platzner (FPL, 2008)

Advanced techniques for the creation and propagation of modules in cartesian genetic programming. - Paul Kaufmann; Marco Platzner (GECCO, 2008)

A Comparison of Evolvable Hardware Architectures for Classification Tasks. - Kyrre Glette; Jim Tørresen; Paul Kaufmann; Marco Platzner (ICES, 2008)

On Robust Evolution of Digital Hardware. - Tobias Knieper; Bertrand Defo; Paul Kaufmann; Marco Platzner (BICC, 2008)

Realizing reconfigurable mesh algorithms on softcore arrays. - Heiner Giefers; Marco Platzner (ICSAMOS, 2008)

EvoCaches: Application-specific Adaptation of Cache Mappings. - Paul Kaufmann; Christian Plessl; Marco Platzner (AHS, 2009)

A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms. - Markus Happe; Enno Lübbers; Marco Platzner (ARC, 2009)

IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. - Tobias Schumacher 001; Christian Plessl; Marco Platzner (FCCM, 2009)

Program-driven fine-grained power management for the reconfigurable mesh. - Heiner Giefers; Marco Platzner (FPL, 2009)

Cooperative multithreading in dynamically reconfigurable systems. - Enno Lübbers; Marco Platzner (FPL, 2009)

An accelerator for K-TH nearest neighbor thinning based on the IMORC infrastructure. - Tobias Schumacher 001; Christian Plessl; Marco Platzner (FPL, 2009)

ARMLang: A language and compiler for programming reconfigurable mesh many-cores. - Heiner Giefers; Marco Platzner (IPDPS, 2009)

Proof-Carrying Hardware: Towards Runtime Verification of Reconfigurable Modules. - Stephanie Drzevitzky; Uwe Kastens; Marco Platzner (ReConFig, 2009)

Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000. - Tobias Schumacher 001; Tim Süß; Christian Plessl; Marco Platzner (ReConFig, 2009)

ReconOS: Multithreaded programming for reconfigurable computers. - Enno Lübbers; Marco Platzner (ACM Trans. Embed. Comput. Syst., 2009)

ReconOS: An Operating System for Dynamically Reconfigurable Hardware. - Enno Lübbers; Marco Platzner (Dynamically Reconfigurable Systems, 2010)

A novel hybrid evolutionary strategy and its periodization with multi-objective genetic optimizers. - Paul Kaufmann; Tobias Knieper; Marco Platzner (IEEE Congress on Evolutionary Computation, 2010)

A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics. - Heiner Giefers; Marco Platzner (ERSA, 2010)

Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware. - Enno Lübbers; Marco Platzner; Christian Plessl; Ariane Keller; Bernhard Plattner (ERSA, 2010)

A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier. - Heiner Giefers; Marco Platzner (FPL, 2010)

Coping with Resource Fluctuations: The Run-time Reconfigurable Functional Unit Row Classifier Architecture. - Tobias Knieper; Paul Kaufmann; Kyrre Glette; Marco Platzner; Jim Tørresen (ICES, 2010)

Engineering self-coordinating software intensive systems. - Wilhelm Schäfer; Mauro Birattari; Johannes Blömer; Marco Dorigo; Gregor Engels; Rehan O'Grady; Marco Platzner; Franz-Josef Rammig; Wolfgang Reif; Ansgar Trächtler (FoSER, 2010)

Selected papers from the 18th International Conference on Field Programmable Logic and Applications (FPL 2008) [Editorial]. - Udo Kebschull; Marco Platzner; Jürgen Teich (IET Comput. Digit. Tech., 2010)

Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification. - Stephanie Drzevitzky; Uwe Kastens; Marco Platzner (Int. J. Reconfigurable Comput., 2010)

Multi-objective Intrinsic Evolution of Embedded Systems. - Paul Kaufmann; Marco Platzner (Organic Computing, 2011)

Design and architectures for dependable embedded systems. - Jörg Henkel; Lars Bauer; Joachim Becker; Oliver Bringmann 001; Uwe Brinkschulte; Samarjit Chakraborty; Michael Engel; Rolf Ernst; Hermann Härtig; Lars Hedrich; Andreas Herkersdorf; Rüdiger Kapitza; et al. (CODES+ISSS, 2011)

Parallel Monte-Carlo Tree Search for HPC Systems. - Tobias Graf; Ulf Lorenz; Marco Platzner; Lars Schaefers (Euro-Par (2), 2011)

Performance estimation framework for automated exploration of CPU-accelerator architectures. - Tobias Kenter; Christian Plessl; Marco Platzner; Michael Kauschke (FPGA, 2011)

Memory Virtualization for Multithreaded Reconfigurable Hardware. - Andreas Agne; Marco Platzner; Enno Lübbers (FPL, 2011)

Achieving hardware security for reconfigurable systems on chip by a proof-carrying code approach. - Stephanie Drzevitzky; Marco Platzner (ReCoSoC, 2011)

FPGA Acceleration of Communication-Bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study. - Tobias Schumacher 001; Tim Süß; Christian Plessl; Marco Platzner (Int. J. Reconfigurable Comput., 2011)

Evolution of Electronic Circuits. - Lukás Sekanina; James Alfred Walker; Paul Kaufmann; Marco Platzner (Cartesian Genetic Programming, 2011)

Problem Decomposition in Cartesian Genetic Programming. - James Alfred Walker; Julian F. Miller; Paul Kaufmann; Marco Platzner (Cartesian Genetic Programming, 2011)

Comparison of Bayesian move prediction systems for Computer Go. - Martin Wistuba; Lars Schaefers; Marco Platzner (CIG, 2012)

Reducing classification accuracy degradation of pattern recognition based myoelectric control caused by electrode shift using a high density electrode array. - Alexander Boschmann; Marco Platzner (EMBC, 2012)

Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture. - Paul Kaufmann; Kyrre Glette; Marco Platzner; Jim Tørresen (Int. J. Adapt. Resilient Auton. Syst., 2012)

IMORC: An infrastructure and architecture template for implementing high-performance reconfigurable FPGA accelerators. - Tobias Schumacher 001; Christian Plessl; Marco Platzner (Microprocess. Microsystems, 2012)

On Semeai Detection in Monte-Carlo Go. - Tobias Graf; Lars Schaefers; Marco Platzner (Computers and Games, 2013)

Improving transient state myoelectric signal recognition in hand movement classification using gyroscopes. - Alexander Boschmann; Barbara Nofen; Marco Platzner (EMBC, 2013)

On-The-Fly Computing: A novel paradigm for individualized IT services. - Markus Happe; Friedhelm Meyer auf der Heide; Peter Kling; Marco Platzner; Christian Plessl (ISORC, 2013)

Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime. - Jahanzeb Anwer; Sebastian Meisner; Marco Platzner (ReConFig, 2013)

A self-adaptive heterogeneous multi-core architecture for embedded real-time video object tracking. - Markus Happe; Enno Lübbers; Marco Platzner (J. Real Time Image Process., 2013)

Classification of Electromyographic Signals: Comparing Evolvable Hardware to Conventional Classifiers. - Paul Kaufmann; Kyrre Glette; Thiemo Gruber; Marco Platzner; Jim Tørresen; Bernhard Sick (IEEE Trans. Evol. Comput., 2013)

Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores for Error Detection. - Sebastian Meisner; Marco Platzner (ARC, 2014)

Common fate graph patterns in Monte Carlo Tree Search for computer go. - Tobias Graf; Marco Platzner (CIG, 2014)

Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs. - Jahanzeb Anwer; Marco Platzner (DFT, 2014)

Towards robust HD EMG pattern recognition: Reducing electrode displacement effect using structural similarity. - Alexander Boschmann; Marco Platzner (EMBC, 2014)

A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms. - Nam Ho; Paul Kaufmann; Marco Platzner (FPL, 2014)

Memory security in reconfigurable computers: Combining formal verification with monitoring. - Tobias Wiersema; Stephanie Drzevitzky; Marco Platzner (FPT, 2014)

Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure. - Nam Ho; Paul Kaufmann; Marco Platzner (ICES, 2014)

Integrating Software and Hardware Verification. - Marie-Christine Jakobs; Marco Platzner; Heike Wehrheim; Tobias Wiersema (IFM, 2014)

FPGA Redundancy Configurations: An Automated Design Space Exploration. - Jahanzeb Anwer; Marco Platzner; Sebastian Meisner (IPDPS Workshops, 2014)

Embedding FPGA overlays into configurable Systems-on-Chip: ReconOS meets ZUMA. - Tobias Wiersema; Arne Bockhorn; Marco Platzner (ReConFig, 2014)

Seven recipes for setting your FPGA on fire - A cookbook on heat generators. - Andreas Agne; Hendrik Hangmann; Markus Happe; Marco Platzner; Christian Plessl (Microprocess. Microsystems, 2014)

ReconOS: An Operating System Approach for Reconfigurable Computing. - Andreas Agne; Markus Happe; Ariane Keller; Enno Lübbers; Bernhard Plattner; Marco Platzner; Christian Plessl (IEEE Micro, 2014)

An FPGA-Based Reconfigurable Mesh Many-Core. - Heiner Giefers; Marco Platzner (IEEE Trans. Computers, 2014)

Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores. - Andreas Agne; Markus Happe; Achim Lösch; Christian Plessl; Marco Platzner (ACM Trans. Reconfigurable Technol. Syst., 2014)

Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement Learning. - Tobias Graf; Marco Platzner (ACG, 2015)

Microarchitectural optimization by means of reconfigurable and evolvable cache mappings. - Nam Ho; Abdullah Fathi Ahmed; Paul Kaufmann; Marco Platzner (AHS, 2015)

On-The-Fly Verification of Reconfigurable Image Processing Modules Based on a Proof-Carrying Hardware Approach. - Tobias Wiersema; Sen Wu 005; Marco Platzner (ARC, 2015)

Significant papers from the first 25 years of the FPL conference. - Philip Heng Wai Leong; Hideharu Amano; Jason Helge Anderson; Koen Bertels; João M. P. Cardoso; Oliver Diessel; Guy Gogniat; Mike Hutton; JunKyu Lee; Wayne Luk; Patrick Lysaght; Marco Platzner; et al. (FPL, 2015)

Comparison of thread signatures for error detection in hybrid multi-cores. - Sebastian Meisner; Marco Platzner (FPT, 2015)

FPGA-based acceleration of high density myoelectric signal processing. - Alexander Boschmann; Andreas Agne; Linus Witschen; Georg Thombansen; Florian Kraus; Marco Platzner (ReConFig, 2015)

Approximate Computing. - Christian Plessl; Marco Platzner; Peter J. Schreier (Inform. Spektrum, 2015)

Distributed Monte Carlo Tree Search: A Novel Technique and its Application to Computer Go. - Lars Schaefers; Marco Platzner (IEEE Trans. Comput. Intell. AI Games, 2015)

ReconOS. - Andreas Agne; Marco Platzner; Christian Plessl; Markus Happe; Enno Lübbers (FPGAs for Software Programmers, 2016)

Using Deep Convolutional Neural Networks in Monte Carlo Tree Search. - Tobias Graf; Marco Platzner (Computers and Games, 2016)

Monte-Carlo simulation balancing revisited. - Tobias Graf; Marco Platzner (CIG, 2016)

On-the-fly computing: self-aware heterogeneous multi-cores. - Marco Platzner (CODES+ISSS, 2016)

Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. - Achim Lösch; Tobias Beisel; Tobias Kenter; Christian Plessl; Marco Platzner (DATE, 2016)

Boolean Difference Based Reliability Evaluation of Fault-Tolerant Circuit Structures on FPGAs. - Jahanzeb Anwer; Marco Platzner (DSD, 2016)

New Co-design Methodology for Real-time Embedded Systems. - Ines Ghribi; Riadh Ben Abdallah; Mohamed Khalgui; Marco Platzner (ICSOFT-EA, 2016)

I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems. - Ines Ghribi; Riadh Ben Abdallah; Mohamed Khalgui; Marco Platzner (ICSOFT (Selected Papers), 2016)

Thread shadowing: On the effectiveness of error detection at the hardware thread level. - Sebastian Meisner; Marco Platzner (ReConFig, 2016)

Programming models for reconfigurable manycore systems. - David Andrews 001; Marco Platzner (ReCoSoC, 2016)

Verifying worst-case completion times for reconfigurable hardware modules using proof-carrying hardware. - Tobias Wiersema; Marco Platzner (ReCoSoC, 2016)

An architecture and design tool flow for embedding a virtual FPGA into a reconfigurable system-on-chip. - Tobias Wiersema; Arne Bockhorn; Marco Platzner (Comput. Electr. Eng., 2016)

Adaptive playouts for online learning of policies during Monte Carlo Tree Search. - Tobias Graf; Marco Platzner (Theor. Comput. Sci., 2016)

Self-aware Compute Nodes. - Andreas Agne; Markus Happe; Achim Lösch; Christian Plessl; Marco Platzner (Self-aware Computing Systems, 2016)

Self-aware Computing: Introduction and Motivation. - Peter R. Lewis 001; Marco Platzner; Bernhard Rinner; Jim Tørresen; Xin Yao 001 (Self-aware Computing Systems, 2016)

Conclusions and Outlook. - Peter R. Lewis 001; Marco Platzner; Bernhard Rinner; Jim Tørresen; Xin Yao 001 (Self-aware Computing Systems, 2016)

Evaluation methodology for complex non-deterministic functions: A case study in metaheuristic optimization of caches. - Paul Kaufmann; Nam Ho; Marco Platzner (AHS, 2017)

reMinMin: A novel static energy-centric list scheduling approach based on real measurements. - Achim Lösch; Marco Platzner (ASAP, 2017)

A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller. - Alexander Boschmann; Georg Thombansen; Linus Witschen; Alex Wiens; Marco Platzner (DATE, 2017)

Accurate private/shared classification of memory accesses: A run-time analysis system for the LEON3 multi-core processor. - Nam Ho; Ishraq Ibne Ashraf; Paul Kaufmann; Marco Platzner (DATE, 2017)

Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor. - Nam Ho; Paul Kaufmann; Marco Platzner (FPT, 2017)

Adaptable Realization of Industrial Analytics Functions on Edge-Devices using Reconfigurable Architectures. - Carlos Paiz Gatica; Marco Platzner (ML4CPS, 2017)

Computational self-awareness as design approach for visual sensor nodes. - Zakarya Guettatfi; Philipp Hübner; Marco Platzner; Bernhard Rinner (ReCoSoC, 2017)

Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus. - Jahanzeb Anwer; Marco Platzner (Microprocess. Microsystems, 2017)

Guest Editorial: IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing Joint Special Section on Innovation in Reconfigurable Computing Fabrics from Devices to Architectures. - Ronald F. DeMara; Marco Platzner; Marco Ottavi (IEEE Trans. Emerg. Top. Comput., 2017)

Proof-Carrying Hardware via Inductive Invariants. - Tobias Isenberg 002; Marco Platzner; Heike Wehrheim; Tobias Wiersema (ACM Trans. Design Autom. Electr. Syst., 2017)

The First 25 Years of the FPL Conference: Significant Papers. - Philip Heng Wai Leong; Hideharu Amano; Jason Helge Anderson; Koen Bertels; João M. P. Cardoso; Oliver Diessel; Guy Gogniat; Mike Hutton; JunKyu Lee; Wayne Luk; Patrick Lysaght; Marco Platzner; et al. (ACM Trans. Reconfigurable Technol. Syst., 2017)

An FPGA/HMC-Based Accelerator for Resolution Proof Checking. - Tim Hansmeier; Marco Platzner; David Andrews 001 (ARC, 2018)

Ampehre: An Open Source Measurement Framework for Heterogeneous Compute Nodes. - Achim Lösch; Alex Wiens; Marco Platzner (ARCS, 2018)

A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes. - Achim Lösch; Marco Platzner (ASAP, 2018)

An MCTS-based Framework for Synthesis of Approximate Circuits. - Muhammad Awais 009; Hassan Ghasemzadeh Mohammadi; Marco Platzner (VLSI-SoC, 2018)

R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints. - Ines Ghribi; Riadh Ben Abdallah; Mohamed Khalgui; Zhiwu Li 001; Khalid Abdulaziz Alnowibet; Marco Platzner (IEEE Access, 2018)

Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan. - Qazi Arbab Ahmed; Tobias Wiersema; Marco Platzner (ARC, 2019)

Jump Search: A Fast Technique for the Synthesis of Approximate Circuits. - Linus Witschen; Hassan Ghasemzadeh Mohammadi; Matthias Artmann; Marco Platzner (ACM Great Lakes Symposium on VLSI, 2019)

An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware. - Zakarya Guettatfi; Marco Platzner; Omar Kermia; Abdelhakim Khouas (IPDPS Workshops, 2019)

Optimization of Application-Specific L1 Cache Translation Functions of the LEON3 Processor. - Nam Ho; Paul Kaufmann; Marco Platzner (SoCPaR, 2019)

FPGAs im Rechenzentrum. - Marco Platzner; Christian Plessl (Inform. Spektrum, 2019)

Zynq-based acceleration of robust high density myoelectric signal processing. - Alexander Boschmann; Andreas Agne; Georg Thombansen; Linus Witschen; Florian Kraus; Marco Platzner (J. Parallel Distributed Comput., 2019)

An Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology. - Tim Hansmeier; Marco Platzner; Md Jubaer Hossain Pantho; David Andrews 001 (J. Signal Process. Syst., 2019)

Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices. - Zakarya Guettatfi; Paul Kaufmann; Marco Platzner (ARC, 2020)

DeepWind: An Accurate Wind Turbine Condition Monitoring Framework via Deep Learning on Embedded Platforms. - Hassan Ghasemzadeh Mohammadi; Rahil Arshad; Sneha Rautmare; Suraj Manjunatha; Maurice Kuschel; Felix Paul Jentzsch; Marco Platzner; Alexander Boschmann; Dirk Schollbach (ETFA, 2020)

Enabling XCSF to cope with dynamic environments via an adaptive error threshold. - Tim Hansmeier; Paul Kaufmann; Marco Platzner (GECCO Companion, 2020)

An adaption mechanism for the error threshold of XCSF. - Tim Hansmeier; Paul Kaufmann; Marco Platzner (GECCO Companion, 2020)

A Hybrid Synthesis Methodology for Approximate Circuits. - Muhammad Awais 009; Hassan Ghasemzadeh Mohammadi; Marco Platzner (ACM Great Lakes Symposium on VLSI, 2020)

ReconROS: Flexible Hardware Acceleration for ROS2 Applications. - Christian Lienen; Marco Platzner; Bernhard Rinner (FPT, 2020)

MigHEFT: DAG-based Scheduling of Migratable Tasks on Heterogeneous Compute Nodes. - Achim Lösch; Marco Platzner (IPDPS Workshops, 2020)

Evolution of application-specific cache mappings. - Nam Ho; Paul Kaufmann; Marco Platzner (Int. J. Hybrid Intell. Syst., 2020)

Dynamic Reliability Management for FPGA-Based Systems. - Jahanzeb Anwer; Sebastian Meisner; Marco Platzner (Int. J. Reconfigurable Comput., 2020)

Self-aware Cyber-Physical Systems. - Kirstie L. Bellman; Christopher Landauer; Nikil D. Dutt; Lukas Esterle; Andreas Herkersdorf; Axel Jantsch; Nima Taherinejad; Peter R. Lewis 001; Marco Platzner; Kalle Tammemäe (ACM Trans. Cyber Phys. Syst., 2020)

Proof-Carrying Approximate Circuits. - Linus Witschen; Tobias Wiersema; Marco Platzner (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Timing Optimization for Virtual FPGA Configurations. - Linus Witschen; Tobias Wiersema; Masood Raeisi Nafchi; Arne Bockhorn; Marco Platzner (ARC, 2021)

Malicious Routing: Circumventing Bitstream-level Verification for FPGAs. - Qazi Arbab Ahmed; Tobias Wiersema; Marco Platzner (DATE, 2021)

An experimental comparison of explore/exploit strategies for the learning classifier system XCS. - Tim Hansmeier; Marco Platzner (GECCO Companion, 2021)

LDAX: A Learning-based Fast Design Space Exploration Framework for Approximate Circuit Synthesis. - Muhammad Awais 009; Hassan Ghasemzadeh Mohammadi; Marco Platzner (ACM Great Lakes Symposium on VLSI, 2021)

MCTS-based Synthesis Towards Efficient Approximate Accelerators. - Muhammad Awais 009; Marco Platzner (ISVLSI, 2021)

FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics. - Hassan Ghasemzadeh Mohammadi; Felix Paul Jentzsch; Maurice Kuschel; Rahil Arshad; Sneha Rautmare; Suraj Manjunatha; Marco Platzner; Alexander Boschmann; Dirk Schollbach (PKDD/ECML Workshops (1), 2021)

Software/Hardware Co-Verification for Custom Instruction Set Processors. - Marie-Christine Jakobs; Felix Pauck; Marco Platzner; Heike Wehrheim; Tobias Wiersema (IEEE Access, 2021)

Search space characterization for approximate logic synthesis. - Linus Witschen; Tobias Wiersema; Lucas Reuter; Marco Platzner (DAC, 2022)

MUSCAT: MUS-based Circuit Approximation Technique. - Linus Witschen; Tobias Wiersema; Matthias Artmann; Marco Platzner (DATE, 2022)

Event-Driven Programming of FPGA-accelerated ROS 2 Robotics Applications. - Christian Lienen; Marco Platzner (DSD, 2022)

Integrating Safety Guarantees into the Learning Classifier System XCS. - Tim Hansmeier; Marco Platzner (EvoApplications, 2022)

XCS on embedded systems: an analysis of execution profiles and accelerated classifier deletion. - Mathis Brede; Tim Hansmeier; Marco Platzner (GECCO Companion, 2022)

ReconOS64: A Hardware Operating System for Modern Platform FPGAs with 64-Bit Support. - Lennart Clausing; Marco Platzner (IPDPS Workshops, 2022)

Task Mapping for Hardware-Accelerated Robotics Applications using ReconROS. - Christian Lienen; Marco Platzner (IRC, 2022)

On the Detection and Circumvention of Bitstream-level Trojans in FPGAs. - Qazi Arbab Ahmed; Marco Platzner (ISVLSI, 2022)

Automated Framework for Fast Synthesis of Approximate Hardware Accelerators. - Muhammad Awais 009; Marco Platzner (VLSI-SoC, 2022)

ReconROS Executor: Event-Driven Programming of FPGA-accelerated ROS 2 Applications. - Christian Lienen; Marco Platzner (CoRR, 2022)

RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures. - Felix Jentzsch; Yaman Umuroglu; Alessandro Pappalardo; Michaela Blott; Marco Platzner (IEEE Micro, 2022)

Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs. - Alfonso Rodríguez 002; Andrés Otero; Marco Platzner; Eduardo de la Torre (IEEE Trans. Computers, 2022)

Design of Distributed Reconfigurable Robotics Systems with ReconROS. - Christian Lienen; Marco Platzner (ACM Trans. Reconfigurable Technol. Syst., 2022)

On Guaranteeing Schedulability of Periodic Real-Time Hardware Tasks Under ReconOS64. - Lennart Clausing; Zakarya Guettatfi; Paul Kaufmann; Christian Lienen; Marco Platzner (ARC, 2023)

Mapping and Optimizing Communication in ROS 2-based Applications on Configurable System-on-Chip Platforms. - Christian Lienen; Alexander Philipp Nowosad; Marco Platzner (ICRAI, 2023)

AutonomROS: A ReconROS-based Autonomous Driving Unit. - Christian Lienen; Mathis Brede; Daniel Karger; Kevin Koch; Dalisha Logan; Janet Mazur; Alexander Philipp Nowosad; Alexander Schnelle; Mohness Waizy; Marco Platzner (IRC, 2023)

FPGADDS: An Intra-FPGA Data Distribution Service for ROS 2 Robotics Applications. - Christian Lienen; Sorel Horst Middeke; Marco Platzner (IROS, 2023)

MAAS: Hiding Trojans in Approximate Circuits. - Qazi Arbab Ahmed; Muhammad Awais 009; Marco Platzner (ISQED, 2023)

AutonomROS: A ReconROS-based Autonomonous Driving Unit. - Christian Lienen; Mathis Brede; Daniel Karger; Kevin Koch; Dalisha Logan; Janet Mazur; Alexander Philipp Nowosad; Alexander Schnelle; Mohness Waizy; Marco Platzner (CoRR, 2023)

FINN-T: Compiling Custom Dataflow Accelerators for Quantized Transformers. - Christoph Berganski; Felix Jentzsch; Marco Platzner; Max Kuhmichel; Heiner Giefers (ICFPT, 2024)

DeepApprox: Rapid Deep Learning based Design Space Exploration of Approximate Circuits via Check-pointing. - Muhammad Awais 009; Hassan Ghasemzadeh Mohammadi; Marco Platzner (ISVLSI, 2024)

Post-configuration Activation of Hardware Trojans in FPGAs. - Qazi Arbab Ahmed; Tobias Wiersema; Marco Platzner (J. Hardw. Syst. Secur., 2024)

Correction to: Post-configuration Activation of Hardware Trojans in FPGAs. - Qazi Arbab Ahmed; Tobias Wiersema; Marco Platzner (J. Hardw. Syst. Secur., 2024)

Ultra-Low Latency and Extreme-Throughput Echo State Neural Networks on FPGA. - Atousa Jafari; Marco Platzner (ARC, 2025)

A Two-Stage Approximation Methodology for Efficient DNN Hardware Implementation. - Amir Hossein Hadipour; Atousa Jafari; Muhammad Awais 009; Marco Platzner (DDECS, 2025)

Deep&Wide: Achieving Area Efficiency in Scalable Approximate Accelerators. - Farjana Jalil; Muhammad Awais 009; Qazi Arbab Ahmed; Hassan Ghasemzadeh Mohammadi; Thorsten Jungeblut; Marco Platzner (DSN-W, 2025)

Design Space Exploration for Approximate Circuits via Checkpointing and DNN-Based Estimators. - Muhammad Awais 009; Hassan Ghasemzadeh Mohammadi; Marco Platzner (IEEE Trans. Very Large Scale Integr. Syst., 2025)