A Flexible Debugger for a RISC-V Based 32-bit System-on-Chip. - Wilmer Ramirez; Marco Sarmiento; Elkim Roa (LASCAS, 2020)

System-on-Chip Implementation of Trusted Execution Environment with Heterogeneous Architecture. - Trong-Thuc Hoang; Ckristian Duran; Ronaldo Serrano; Marco Sarmiento; Khai-Duy Nguyen; Akira Tsukamoto; Kuniyasu Suzaki; Cong-Kha Pham (HCS, 2021)

ChaCha20-Poly1305 Crypto Core Compatible with Transport Layer Security 1.3. - Ronaldo Serrano; Ckristian Duran; Trong-Thuc Hoang; Marco Sarmiento; Akira Tsukamoto; Kuniyasu Suzaki; Cong-Kha Pham (ISOCC, 2021)

A Low-Power Low-Area SoC based in RISC-V Processor for IoT Applications. - Ronaldo Serrano; Marco Sarmiento; Ckristian Duran; Khai-Duy Nguyen; Trong-Thuc Hoang; Koichiro Ishibashi; Cong-Kha Pham (ISOCC, 2021)

A Fully Digital True Random Number Generator With Entropy Source Based in Frequency Collapse. - Ronaldo Serrano; Ckristian Duran; Trong-Thuc Hoang; Marco Sarmiento; Khai-Duy Nguyen; Akira Tsukamoto; Kuniyasu Suzaki; Cong-Kha Pham (IEEE Access, 2021)

A Sub-μ W Reversed-Body-Bias 8-bit Processor on 65-nm Silicon-on-Thin-Box (SOTB) for IoT Applications. - Marco Sarmiento; Khai-Duy Nguyen; Ckristian Duran; Trong-Thuc Hoang; Ronaldo Serrano; Van-Phuc Hoang; Xuan-Tu Tran; Koichiro Ishibashi; Cong-Kha Pham (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 3.65 Gb/s Area-Efficiency ChaCha20 Cryptocore. - Ronaldo Serrano; Marco Sarmiento; Ckristian Duran; Trong-Thuc Hoang; Cong-Kha Pham (ISOCC, 2022)

Trusted Execution Environment Hardware by Isolated Heterogeneous Architecture for Key Scheduling. - Trong-Thuc Hoang; Ckristian Duran; Ronaldo Serrano; Marco Sarmiento; Khai-Duy Nguyen; Akira Tsukamoto; Kuniyasu Suzaki; Cong-Kha Pham (IEEE Access, 2022)

A Robust and Healthy Against PVT Variations TRNG Based on Frequency Collapse. - Ronaldo Serrano; Ckristian Duran; Marco Sarmiento; Trong-Thuc Hoang; Akira Tsukamoto; Kuniyasu Suzaki; Cong-Kha Pham (IEEE Access, 2022)

A Unified NVRAM and TRNG in Standard CMOS Technology. - Ronaldo Serrano; Ckristian Duran; Marco Sarmiento; Cong-Kha Pham (IEEE Access, 2022)

ChaCha20-Poly1305 Authenticated Encryption with Additional Data for Transport Layer Security 1.3. - Ronaldo Serrano; Ckristian Duran; Marco Sarmiento; Cong-Kha Pham; Trong-Thuc Hoang (Cryptogr., 2022)

A Unified PUF and Crypto Core Exploiting the Metastability in Latches. - Ronaldo Serrano; Ckristian Duran; Marco Sarmiento; Tuan-Kiet Dang; Trong-Thuc Hoang; Cong-Kha Pham (Future Internet, 2022)

Systems on a Chip With 8 and 32 Bits Processors in 0.18-μm Technology for IoT Applications. - Marco Sarmiento; Khai-Duy Nguyen; Ckristian Duran; Ronaldo Serrano; Trong-Thuc Hoang; Koichiro Ishibashi; Cong-Kha Pham (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

In-NVRAM Unified PUF and TRNG Based on Standard CMOS Technology. - Ronaldo Serrano; Marco Sarmiento; Ckristian Duran; Tuan-Kiet Dang; Trong-Thuc Hoang; Cong-Kha Pham (ISCAS, 2023)

A Unified OTP and PUF Exploiting Post-Program Current on Standard CMOS Technology. - Ronaldo Serrano; Ckristian Duran; Marco Sarmiento; Khai-Duy Nguyen; Tetsuya Iizuka; Trong-Thuc Hoang; Cong-Kha Pham (ISCAS, 2024)