A 750mV 15kHz 1/f Noise Corner 51dBm IIP2 Direct-Conversion Front-End for GSM in 90nm CMOS. - Massimo Brandolini; Marco Sosio; Francesco Svelto (ISSCC, 2006)

A 750 mV Fully Integrated Direct Conversion Receiver Front-End for GSM in 90-nm CMOS. - Massimo Brandolini; Marco Sosio; Francesco Svelto (IEEE J. Solid State Circuits, 2007)

A 24GHz Sub-Harmonic Receiver Front-End with Integrated Multi-Phase LO Generation in 65nm CMOS. - Andrea Mazzanti; Marco Sosio; Matteo Repossi; Francesco Svelto (ISSCC, 2008)

A reconfigurable demodulator with 3-to-5GHz agile synthesizer for 9-band WiMedia UWB in 65nm CMOS. - Andrea Mazzanti; Mohammad B. Vahidfar; Marco Sosio; Francesco Svelto (ISSCC, 2009)

A Low Phase-Noise Multi-Phase LO Generator for Wideband Demodulators Based on Reconfigurable Sub-Harmonic Mixers. - Andrea Mazzanti; Mohammad B. Vahidfar; Marco Sosio; Francesco Svelto (IEEE J. Solid State Circuits, 2010)

A complete DVB-T/ATSC tuner analog base-band implemented with a single filtering ADC. - Marco Sosio; Antonio Liscidini; Rinaldo Castello; Fernando De Bernardinis (ESSCIRC, 2011)

A 24 GHz Subharmonic Direct Conversion Receiver in 65 nm CMOS. - Andrea Mazzanti; Marco Sosio; Matteo Repossi; Francesco Svelto (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

A 40MHz-to-1GHz fully integrated multistandard silicon tuner in 80nm CMOS. - Jody Greenberg; Fernando De Bernardinis; Carlo Tinella; Antonio Milani; Johnny Pan; Paola Uggetti; Marco Sosio; Shaoan Dai; Sam Tang; Giovanni Cesura; Gabriele Gandolfi; Vittorio Colonna; et al. (ISSCC, 2012)

A 2G/3G Cellular Analog Baseband Based on a Filtering ADC. - Marco Sosio; Antonio Liscidini; Rinaldo Castello (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

SAW-Less Analog Front-End Receivers for TDD and FDD. - Ivan Fabiano; Marco Sosio; Antonio Liscidini; Rinaldo Castello (IEEE J. Solid State Circuits, 2013)

A 40-MHz-to-1-GHz Fully Integrated Multistandard Silicon Tuner in 80-nm CMOS. - Jody Greenberg; Fernando De Bernardinis; Carlo Tinella; Antonio Milani; Johnny Pan; Paola Uggetti; Marco Sosio; Shaoan Dai; Samuel Er-Shen Tang; Giovanni Cesura; Gabriele Gandolfi; Vittorio Colonna; et al. (IEEE J. Solid State Circuits, 2013)

An Intuitive Current-Driven Passive Mixer Model Based on Switched-Capacitor Theory. - Marco Sosio; Antonio Liscidini; Rinaldo Castello (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

Impact of CMOS Scaling on Switched-Capacitor Power Amplifiers. - Alessandro Truppi; Carlo Samori; Andrea L. Lacaita; Salvatore Levantino; Marco Ronchi; Marco Sosio (ISCAS, 2018)

A Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB IL ADC/DAC-Based Transceiver in 7nm FinFET. - Matteo Pisati; Fernando De Bernardinis; Paolo Pascale; Claudio Nani; Marco Sosio; Enrico Pozzati; Nicola Ghittori; Federico Magni; Marco Garampazzi; Giacomino Bollati; Antonio Milani; Alberto Minuti; et al. (ISSCC, 2019)

A 243-mW 1.25-56-Gb/s Continuous Range PAM-4 42.5-dB IL ADC/DAC-Based Transceiver in 7-nm FinFET. - Matteo Pisati; Alberto Minuti; Giacomino Bollati; Fabio Giunco; Roberto G. Massolini; Giovanni Cesura; Fernando De Bernardinis; Paolo Pascale; Claudio Nani; Nicola Ghittori; Enrico Pozzati; Marco Sosio; et al. (IEEE J. Solid State Circuits, 2020)

An Integrated Low-power 802.11ba Wake-up Radio for IoT with Embedded Microprocessor. - Marco Ronchi; Francesco Malena; Michele Caselli; Devis Gatti; Ermano Picco; Elena Salurso; Marco Sosio; Lucio Ticli; Alessandro Tomasoni; Eusebio Di-Cola; Tommaso Majo; Fabio Osnato; et al. (ICECS 2022, 2022)

A 800Gb/s Transceiver for PAM-4 Optical Direct-Detection Applications in 5nm FinFet Process. - Fabio Giunco; Marco Sosio; Claudio Nani; Ivan Fabiano; Travis Lovitt; Victor Karam; D. Albano; C. Asero; Nicola Codega; Marco Garampazzi; Nicola Ghittori; D. Herbas; et al. (VLSI Technology and Circuits, 2024)

A 5nm 60GS/s 7b 64-Way Time Interleaved Partial Loop Unrolled SAR ADC Achieving 34dB SNDR up to 32GHz. - Claudio Nani; Enrico Monaco; Nicola Ghittori; Alessandro Bosi; Domenico Albano; Claudio Asero; Nicola Codega; Alessio Di Pasquo; Ivan Fabiano; Marco Garampazzi; Fabio Giunco; Leonardo Daniel Herbas Burgos; et al. (VLSI Technology and Circuits, 2024)

An Eight-Lane 800-Gb/s Transceiver for PAM-4 Optical Direct-Detection Applications in 5-nm FinFET Process. - Fabio Giunco; Marco Sosio; Claudio Nani; Ivan Fabiano; Travis Lovitt; Victor Karam; Domenico Albano; Claudio Asero; Nicola Codega; Marco Garampazzi; Nicola Ghittori; Leonardo Daniel Herbas Burgos; et al. (IEEE J. Solid State Circuits, 2025)

A 5-nm 60-GS/s 7b 64-Way Time Interleaved Partial Loop Unrolled SAR ADC Achieving 35.2dB SNDR up to 32 GHz. - Claudio Nani; Enrico Monaco; Nicola Ghittori; Alessandro Bosi; Domenico Albano; Claudio Asero; Nicola Codega; Alessio Di Pasquo; Ivan Fabiano; Marco Garampazzi; Fabio Giunco; Leonardo Daniel Herbas Burgos; et al. (IEEE J. Solid State Circuits, 2025)