M. Spaziani Brunella

Orcid: 0000-0001-8448-0432

According to our database1, M. Spaziani Brunella authored at least 8 papers between 2017 and 2023.

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Bibliography

2023
CPU-free Computing: A Vision with a Blueprint.
Proceedings of the 19th Workshop on Hot Topics in Operating Systems, 2023

2022
Hyperion: A Case for Unified, Self-Hosting, Zero-CPU Data-Processing Units (DPUs).
CoRR, 2022

hXDP: Efficient software packet processing on FPGA NICs.
Commun. ACM, 2022

Faster Software Packet Processing on FPGA NICs with eBPF Program Warping.
Proceedings of the 2022 USENIX Annual Technical Conference, 2022

2019
FlowBlaze: Stateful Packet Processing in Hardware.
Proceedings of the 16th USENIX Symposium on Networked Systems Design and Implementation, 2019

Foreshadow-VMM: Feasibility and Network Perspective.
Proceedings of the 5th IEEE Conference on Network Softwarization, 2019

2018
V- PMP: A VLIW Packet Manipulator Processor.
Proceedings of the 2018 European Conference on Networks and Communications, 2018

2017
Robust throughput boosting for low latency dynamic partial reconfiguration.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017


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