Assessing the suitability of the NGMP multi-core processor in the space domain. - Mikel Fernández; Roberto Gioiosa; Eduardo Quiñones; Luca Fossati; Marco Zulianello; Francisco J. Cazorla (EMSOFT, 2012)

Deconstructing bus access control policies for Real-Time multicores. - Javier Jalle; Jaume Abella 001; Eduardo Quiñones; Luca Fossati; Marco Zulianello; Francisco J. Cazorla (SIES, 2013)

AHRB: A high-performance time-composable AMBA AHB bus. - Javier Jalle; Jaume Abella 001; Eduardo Quiñones; Luca Fossati; Marco Zulianello; Francisco J. Cazorla (RTAS, 2014)

A Dual-Criticality Memory Controller (DCmc): Proposal and Evaluation of a Space Case Study. - Javier Jalle; Eduardo Quiñones; Jaume Abella 001; Luca Fossati; Marco Zulianello; Francisco J. Cazorla (RTSS, 2014)

Seeking Time-Composable Partitions of Tasks for COTS Multicore Processors. - Gabriel Fernandez 002; Jaume Abella 001; Eduardo Quiñones; Luca Fossati; Marco Zulianello; Tullio Vardanega; Francisco J. Cazorla (ISORC, 2015)

Introduction to partial time composability for COTS multicores. - Gabriel Fernandez 002; Jaume Abella 001; Eduardo Quiñones; Tullio Vardanega; Luca Fossati; Marco Zulianello; Francisco J. Cazorla (SAC, 2015)

Contention-aware performance monitoring counte support for real-time MPSoCs. - Javier Jalle; Mikel Fernández; Jaume Abella 001; Jan Andersson; Mathieu Patte; Luca Fossati; Marco Zulianello; Francisco J. Cazorla (SIES, 2016)

Data Bus Slicing for Contention-Free Multicore Real-Time Memory Systems. - Javier Jalle; Eduardo Quiñones; Jaume Abella 001; Luca Fossati; Marco Zulianello; Francisco J. Cazorla (SIES, 2016)