Fully Parameterized Discrete Wavelet Packet Transform Architecture Oriented to FPGA. - Guillermo Payá Vayá; Marcos Martínez Peiró; Francisco José Ballester-Merelo; Francisco José Mora Mas (FPL, 2003)

A new inverse discrete wavelet packet transform architecture. - Guillermo Payá Vayá; Marcos Martínez Peiró; Francisco José Ballester-Merelo; Vicente Herrero-Bosch; Joaquín Cerdá (ISSPA (2), 2003)

2D-DCT Implementation on FPGA by Polynomial Transformation in Two-Dimensions. - Arturo Méndez Patiño; Marcos Martínez Peiró (VLSI-SOC, 2003)

FPGA Custom DSP for ECG Signal Analysis and Compression. - Marcos Martínez Peiró; Francisco José Ballester-Merelo; Guillermo Payá Vayá; Ricardo José Colom-Palero; Rafael Gadea Gironés; J. Belenguer (FPL, 2004)

Architectures for ICT on FPGA. - Arturo Méndez Patiño; Marcos Martínez Peiró; Francisco José Ballester-Merelo; Guillermo Payá Vayá (FPT, 2004)

2D-DCT on FPGA by polynomial transformation in two-dimensions. - Arturo Méndez Patiño; Marcos Martínez Peiró; Francisco José Ballester-Merelo; Guillermo Payá Vayá (ISCAS (3), 2004)

Flexible architecture for the implementation of the two-dimensional discrete wavelet transform (2D-DWT) oriented to FPGA devices. - Ricardo José Colom-Palero; Rafael Gadea Gironés; Francisco José Ballester-Merelo; Marcos Martínez Peiró (Microprocess. Microsystems, 2004)

An active methodology for teaching electronic systems design. - Joaquín Cerdá-Boluda; Marcos Martínez Peiró; Miguel A. Larrea Torres; Rafael Gadea Gironés; Ricardo José Colom-Palero (IEEE Trans. Educ., 2006)

Integer-pixel motion estimation H.264/AVC accelerator architecture with optimal memory management. - Armando Mora Campos; Francisco José Ballester-Merelo; Marcos Martínez Peiró; José A. Canals Esteve (Microprocess. Microsystems, 2008)

Real-Time Early Warning System Design for Pluvial Flash Floods - A Review. - Melisa Acosta-Coll; Francisco José Ballester-Merelo; Marcos Martínez Peiró; Emiro De la Hoz-Franco (Sensors, 2018)