An 8-ns random cycle embedded RAM macro with dual-port interleaved DRAM architecture (D2/RAM). - Yasuhiro Agata; Kenji Motomochi; Yoshifumi Fukushima; Masanori Shirahama; Marefusa Kurumada; Naoki Kuroda; Hiroyuki Sadakata; Kohtaro Hayashi; Toshio Yamada; Kazunari Takahashi; Tsutomu Fujita (IEEE J. Solid State Circuits, 2000)

A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues. - Satoshi Ishikura; Marefusa Kurumada; Toshio Terano; Yoshinobu Yamagami; Naoki Kotani; Katsuji Satomi; Koji Nii; Makoto Yabuuchi; Yasumasa Tsukamoto; Shigeki Ohbayashi; Toshiyuki Oashi; Hiroshi Makino; et al. (IEEE J. Solid State Circuits, 2008)