A Highly Accurate and Parallel Vision MLP FPGA Accelerator based on FP7/8 SIMD Operations. - Mari Yasunaga; Junnosuke Suzuki; Masato Watanabe; Kazushi Kawamura; Thiem Van Chu; Jaehoon Yu; Masato Motomura (MCSoC, 2023)

Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge. - Junnosuke Suzuki; Jaehoon Yu; Mari Yasunaga; Ángel López García-Arias; Yasuyuki Okoshi; Shungo Kumazawa; Kota Ando; Kazushi Kawamura; Thiem Van Chu; Masato Motomura (VLSI Technology and Circuits, 2023)

Progressive Variable Precision DNN With Bitwise Ternary Accumulation. - Junnosuke Suzuki; Mari Yasunaga; Kazushi Kawamura; Thiem Van Chu; Masato Motomura (AICAS, 2024)

High Throughput Datapath Design for Vision Permutator FPGA Accelerator. - Mari Yasunaga; Junnosuke Suzuki; Masato Watanabe; Kazushi Kawamura; Thiem Van Chu; Masato Motomura (ICCE, 2024)

Pianissimo: A Sub-mW Class DNN Accelerator With Progressively Adjustable Bit-Precision. - Junnosuke Suzuki; Jaehoon Yu; Mari Yasunaga; Ángel López García-Arias; Yasuyuki Okoshi; Shungo Kumazawa; Kota Ando; Kazushi Kawamura; Thiem Van Chu; Masato Motomura (IEEE Access, 2024)